ICST AV9248G-56-T, AV9248F-56-T, ICS9248F-56-T, ICS9248G-56-T Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9248-56

Block Diagram

Frequency Timing Generator for Pentium II Systems

9248-56 Rev E 12/27/00

Pin Configuration

28 pin SSOP and TSSOP

Pentium is a trademark on Intel Corporation.

• Generates the following system clocks:

- 2CPU(2.5V) up to 100MHz.

- 6 PCI(3.3V) @ 33.3MHz (Includes one free running).

- 1 REF clks (3.3V) at 14.318MHz.

- 1 Fixed clock at 48MHz

- 1 Fixed clock at 48 or 24MHz

• Skew characteristics:

- CPU – CPU

<175ps

- PCI – PCI < 500ps

- CPU(early) – PCI = 1.5ns – 4ns.

• Supports Spread Spectrum modulation for CPU and PCI
clocks, 0.5% down spread

• Efficient Power management scheme through stop clocks
and power down modes.

• Uses external 14.318MHz crystal, no external load cap
required for CL=18pF crystal.

• 28 pin 209mil SSOP and 173mil TSSOP

The ICS9248-56 is the Main clock solution for Notebook
designs using the Intel 440BX style chipset. Along with an
SDRAM buffer such as the ICS9179-03, it provides all
necessary clock signals for such a system.

Spread spectrum may be enabled by driving pin 26, SPREAD#
active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification
without resorting to board design iterations or costly shielding.
The ICS9248-56 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.

Power Groups

VDD, GND = PLL core
VDDREF , GNDREF = REF(0:1), X1, X2
VDDPCI, GNDPCI = PCICLK_F , PCICLK (0:4)
VDD48, GND48 = 48MHz, 48/24MHz

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-56

Pin Descriptions

Pin number Pin nam e Type Descript i on

1 GNDREF Power Ground for 14.318 MHz reference clock outputs
2 X1 Input 14.318 MHz crys tal input
3 X2 Output 14.318 MHz crystal output
4 PCICLK_F Output 3.3 V free running P CI clock output, wi l l not be stopped by the PCI_STOP#

5,6, 9,10,11 PCICLK (1: 5) Output 3.3 V P CI c l ock outputs, generat i ng timing requirem ents for Penti um II

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7 GNDPCI Power Ground for PCI cloc k outputs

8 VDDPCI Power 3.3 V power for the PCI clock outputs
12 VDD48 Power 3.3 V power for 48/24 MHz c locks
13 48 MHz Output 3.3 V 48 MHz clock output, fixed frequenc y cloc k ty pi cally used with USB devices

14 TS#/48/24MHz Output

3.3 V 48 or 24 MHz output and Tri-st at e option, ac tive l ow = t ri state mode for test i ng,
act ive high = norm al operat ion

15 G ND48 Power Ground for 48/24 MHz clocks

16 SEL 100/66# Input

control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used t he 66.6 MHz frequency i s selected. If Logic "1" is used, the 100 MHz
frequency i s selected. The PCI cl ock is multi pl exed to run at 33. 3 M Hz for bot h
selected cases.

17 PD# Input

As ynchronous active low input pin used t o power down t he device into a low power
state. The internal clocks are disabled and the VCO and the c ryst al are stopped. The
latency of the power down will not be greater than 3ms.

18 CPU_STOP# Input

As ynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
leas t 3 CP U clock s.

19 VDD Power Isolated 3.3 V power for core
20 PCI-Stop# Input

Sy nchronous active low input used to stop the PCICLK i n active low state. It wil l not

effect P CICLK_F or any other outputs.
21 GND P ower Isolated ground for core
22 GNDL Power Ground for CPU clock out puts

23,24 CPUCLK(1:0) Output 2.5 V CPU clock out puts

25 VDDL Power 2.5 V power for CPU clock outputs
26 SPREAD# Output

Power-on spread s pectrum enable option. Active low = spread spectrum clocking

enable. Active high = spread spectrum clocking di sable.
27 REF0/SEL48# Ou tput

3.3 V 14. 318 M Hz referenc e clock output and power-on 48/24 MHz select option.

Ac tive low = 48 M Hz out put at pin 14. A ctive high = 24 MHz output at pi n 14.
28 V DDREF Power 3.3 V power for 14.318 MHz reference c l ock outputs.

3

ICS9248-56

Select Functions

(Functionality determined by TS# and SEL100/66# pin, see below)

Notes:

1. TCLK is a test clock driven on the X1 (crystal in pin) input during test mode.

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Po wer Management

ICS9248-56 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power
up and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry .
Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.

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4

ICS9248-56

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9248-56. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-56 internally . The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

CPU_STOP# Timing Diagram

CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-56. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist.

This signal is synchronized to the CPUCLKs inside the ICS9248-56.

3. All other clocks continue to run undisturbed.

4. PD# and PCI_STOP# are shown in a high (true) state.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.