ICST AV9248F-168-T, ICS9248F-168-T Datasheet
Integrated
Circuit
Systems, Inc.
ICS9248-168
Third party brands and names are the property of their respective owners.
Block Diagram
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KT133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - CPU clock @ 3.3V
• 7 - SDRAM @ 3.3V
• 8 - PCI @ 3.3V,
• 1 - 48MHz, @ 3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 3 - REF @ 3.3V, 14.318MHz.
Features:
• Up to 153MHz frequency support
• Support power management: CPU stop and Power down
Mode from I
2
C programming.
• Spread spectrum for EMI control
(± 0.25% to ± 0.6% center, or 0 to -0.5% or -1.0% down
spread).
• Uses external 14.318MHz crystal
AMD - K7™ Clock Generator for Mobile System
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1.5X strength through I2C
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
REF0
REF
REF2
GND
GND
VDD
CPUCLK
CPUCLKT0
CPUCLKC0
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
S DATA
1
2
2
2
1
ICS9248-168
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
2SF1SF0SFUPCICPegatnecrePdaerpS
000 00.00133.33daerpSretneC%53.0-/+
001 33.33133.33daerpSretneC%53.0-/+
010 00.00133.33daerpSnwoD%5.0-ot0
011 33.33133.33daerpSnwoD%5.0-ot0
100 00.00133.33daerpSretneC%6.0-/+
10 1 33.33133.33daerpSretneC%6.0-/+
110 00.0900.03daerpSretneC%52.0-/+
111 00.02100.03daerpSretneC%52.0-/+
SEL24_48#
S DATA
SCLK
FS (2:0)
PD#
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (5:0)
PCICLK (6:0)
PCICLK_F
SDRAM_F
CPUCLKT0
CPUCLK
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Stop
Stop
Control
Logic
Config.
Reg.
/ 2
REF (2:0)
SDRAM
DRIVER
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
9248-168 Rev B 01/09/01
2
ICS9248-168
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low .
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3
ICS9248-168
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF , Xtal
4
ICS9248-168
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
tiBnoitpircseDDWP
,2tiB
4:7tiB
tiB
2
tiB
7
tiB
6
tiB
5
tiB
4
KLCUPC
)zHM(
KLCICP
)zHM(
daerpS
egatnecerP
devreseR
10100
00000 00.00133.33daerpSretneC%53.0-/+
00001 33.33133.33daerpSretneC%53.0-/+
00010 00.00133.33daerpSnwoD%5.0-ot0
00011 33.33133.33daerpSnwoD%5.0-ot0
00100 00.00133.33daerpSretneC%6.0-/+
00101 33.33133.33daerpSretneC%6.0-/+
00110 00.0900.03daerpSretneC%52.0-/+
00111 00.02100.03daerpSretneC%52.0-/+
01000 03.00134.33daerpSretneC%53.0-/+
01001 37.33134.33daerpSretneC%53.0-/+
01010 03.00134.33daerpSretneC%06.0-/+
01011 37.33134.33daerpSretneC%06.0-/+
01100 00.10176.33daerpSretneC%53.0-/+
01101 66.43176.33daerpSretneC%53.0-/+
01110 00.20100.43daerpSretneC%53.0-/+
01111 00.63100.43daerpSretneC%53.0-/+
10000 00.30133.43daerpSretneC%53.0-/+
1000 1 33.73133.43daerpSretneC%53.0-/+
100 10 00.40176.43daerpSretneC%53.0-/+
100 11 66.83176.43daerpSretneC%53.0-/+
10 10 0 00.50100.53daerpSretneC%53.0-/+
10 10 1 00.04100.53daerpSretneC%53.0-/+
10 1 10 00.70176.53daerpSretneC%53.0-/+
10 111 66.24176.53daerpSretneC%53.0-/+
11000 00.01176.63daerpSretneC%53.0-/+
1100 1 66.64176.63daerpSretneC%53.0-/+
110 10 00.51133.83daerpSretneC%53.0-/+
110 11 33.35133.83daerpSretneC%53.0-/+
11100 00.00133.33daerpSretneC%05.0-/+
1110 1 33.33133.33daerpSretneC%05.0-/+
11110 00.00133.33daerpSnwoD%0.1-ot0
11111 33.33133.33daerpSnwoD%0.1-ot0
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
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daerpSretneC%52.0±delbanEmurtcepSdaerpS-1
1
0tiB
gninnuR-0
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0
5
ICS9248-168
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB2210SF
6tiB511SF
5tiB412SF
4tiB241 X1=1X5.1=0KLCUPC
3tiB-1 devreseR
2tiB04,141 X1=1X5.1=0C/TKLCUPC
1tiB-1 devreseR
0tiB241 KLCUPC
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB41 F_KLCICP
6tiB511 6KLCICP
5tiB211 5KLCICP
4tiB111 4KLCICP
3tiB011 3KLCICP
2tiB91 2KLCICP
1tiB81 1KLCICP
0tiB51 0KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB721 F_MARDS
5tiB821 5MARDS
4tiB921 4MARDS
3tiB231 3MARDS
2tiB331 2MARDS
1tiB631 1MARDS
0tiB731 0MARDS
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-1 devreseR
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
TIB#NIPDWPNOITPIRCSED
7tiB-1 devreseR
6tiB321 #84_42LES
5tiB221 zHM84
4tiB321 zHM84_42
3tiB8410FER
2tiB7411FER
1tiB6412FER
0tiB-1 devreseR
TIB#NIPDWPNOITPIRCSED
7tiB-0 devreseR
6tiB-0 devreseR
5tiB-0 devreseR
4tiB-0 devreseR
3tiB-0 devreseR
2tiB-1 devreseR
1tiB-1 devreseR
0tiB-0 devreseR
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