ICST AV9248F-143-T, ICS9248F-143-T, ICS9248G-143-T Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-143

Block Diagram

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM II/III

TM

& K6

9248-143 Rev C 7/26/00

Pin Configuration

48-Pin SSOP and TSSOP

* Internal Pull-up Resistor of 120K to VDD

CLK_STOP#

PCI_STOP#

CPU2.5_3.3#

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK_F

CPUCLK [2:0]

SDRAM [7:0]

PCICLK [5:0]
PCICLK_F
PCICLK_E

SDRAM_F

X1

X2

BUFFER IN

XTAL
OSC

PCI
CLOCK
DIVDER

STOP

STOP

STOP

SDATA

SCLK

PD#

FS(0:3)

SEL24_48#

Control

Logic

Config.

Reg.

/ 2

REF[1:0]

LATCH

POR

2

3

8

6

4

4

VDDREF

*SPREAD/REF0

GNDREF

X1
X2

VDDPCI

*CPU2.5_3.3#/PCICLK_F

*FS3/PCICLK0

GNDPCI

*SEL24_48#/PCICLK1

*SELPCIE_6#/PCICLK2

PCICLK3
PCICLK4

VDDPCI

BUFFER IN

GNDPCI

PCICLK5

PCICLK6/

VDDCOR

PCI_STOP#

*PD#

GND48

SDATA

SCLK

PCICLK_E

REF1/FS2*
VDDLCPU
CPUCLK_F
CPUCLK0
GNDLCPU
CPUCLK1
CPUCLK2
CLK_STOP#
GNDSDR
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24_48MHz/FS1*

ICS9248-143

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

Recommended Application:

440BX, MX, VIA Apollo Pro 133, Apollo Pro Media
or MVP4 style chip set, for Note book applications.

Output Features:

 4 - CPUs @ 2.5V/3.3V

including 1 free running CPUCLK_F
 9 - SDRAM @ 3.3V
 7 - PCI @ 3.3V, including 1 free running PCICLK_F
 1 - PCI Early @ 3.3V
 1 - 48MHz, @ 3.3V fixed.
 1 - 24/48MHz @ 3.3V
 2 - REF @3.3V, 14.318MHz.

Features:

 Up to 137MHz frequency support
 97MHz to support high-end AMD processor.
 Support power management: CLK, PCI, stop and Power

down Mode from I

2

C programming.

 Spread spectrum for EMI control

(±.25% & 0 to -0.5% down spread).
 Uses external 14.318MHz crystal
 FS pins for frequency select

Key Specifications:

 CPU Output Jitter @ 2.5V: <300ps
 CPU Output Jitter @ 3.3V: <250ps
 PCI Output Jitter @ 3.3V: <250ps
 CPU Output Skew @ 2.5V: <175ps
 CPU Output Skew @ 3.3V: <175ps
 PCI Output Skew @ 3.3V: <500ps
 PCI Early to PCI Skew @ 3.3V: typ = 3ns

Functionality

3SF2SF1SF0SF

UPC

)zHM(

ICP

)zHM(
0000 76.6633.33
0001 00.00133.33
0010 03.00134.33
0011 33.33133.33
0100 00.50100.53
0101 73.33143.33
0110 00.73152.43
0111 00.5705.73

1000 00.00133.33
1001 00.5976.13
1010 00.7933.23
1011 33.33133.33
1100 00.0900.03
1101 22.6970.23
1110 28.6614.33
1111 05.1905.03

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-143

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

NIP

REBMUN

EMANNIPEPYTNOITPIRCSED

1FERDDVRWPV3.3lanimon,ylppusrewopLATX,feR
2

DAERPS

2,1

NI "no"signidaerps,"hgiH"sitluafedpu-rewoP.tupnielbanemurtcepSdaerpShgiHevitcA

0FERTUO sdaolSUBASIrofreffubREGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41

02#POTS_ICPNI )0=EDOM,edomelibomnI(woltupninehw,level0cigoltaskcolcKLCICPstlaH

,61,9,3

44,04,33

DNGRWPdnuorG

41XNI

kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

52XTUO.zHM813.41yllanimon,tuptuolatsyrC

41,6ICPDDVRWPV3.3lanimonKLCICPdnaF_KLCICProfylppuS

7

#3.3_5.2UPC

2,1

NI .tupnIdehctaL.UPCV3.3=WOL,UPCV5.2=hgiH.V3.3ro5.2siUPCLDDVrehtehwsetacidnI

F_KLCICPTUO .tnemeganamrewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

8

3SF

2,1

NI.tupnIdehctaL.niptcelesycneuqerF

0KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.tuptuokcolcICP

01

#84_42LES

2,1

NIzHM84=woLnehwzHM84ro42rehtiestceleS

1KLCICPTUO )ylraeUPC(wekssn4-1htiwskcolcUPCotsuonorhcnyS.tuptuokcolcICP

11

#6_EICPLES

2,1

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51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
81E_KLCICP/6KLCICPTUO #6_EICPLESybelbatcelestuptuokcolcICPylraerotuptuokcolcICP
91ROCDDVRWPV3.3.erocLLPehtrofniprewoP

12#DP

1

NI

ehT.etatsrewopwolaotniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA

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.sm4nahtretaergebtonlliwnwod

2284DNGRWP.erocLLPdexif&sreffubtuptuozHM84&42ehtrofnipdnuorG

,23,13,92,82

83,73,53,43

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63,03RDSDDVRWP.V3.3lanimon,eroCLLPUPCdnaMARDSrofylppuS

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2

tupnitnarelotV5,tupnilairesC

42KLCSNIIfotupnikcolC

2

tupnitnarelotV5,tupniC

52

zHM84_42TUO01nipybelbatceleskcolctuptuozHM84rozHM42

1SF

2,1

NI.tupnIdehctaL.niptcelesycneuqerF

62

zHM84TUOkcolctuptuozHM84

0SF

2,1

NItupnIdehctaL.niptcelesycneuqerF
7284DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
93F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_KLCNI .wolnevirdnehwlevel"0"cigoltaMARDS&,KLCUPCstlahtupnisuonorhcnysasihT

54,34,24)0:2(KLCUPCTUOUPCLDDVybderewop,stuptuokcolcUPC
64F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF
74UPCLDDVRWPV5.2skcolcUPCrofylppuS

84

1FERTUO.kcolcecnereferzHM813.41

2SF

2,1

NItupnIdehctaL.niptcelesycneuqerF

3

ICS9248-143

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Notes:

1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011.
2, PWD = Power-Up Default

The ICS9248-143 is the single chip clock solution for Notebook designs using thE 440BX, MX, VIA Apollo Pro 133, Apollo Pro
Media or MVP4 style chip set. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-143 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

General Description

tiBnoitpircseDDWP

7tiB

daerpSretneC,noitaludoMmurtcepSdaerpS%52.0±-0

daerpSnwoD%5.0-ot0-1

1

tiB

]4:6,2[

]4:6,2[tiB

KLCUPC

)zHM(

KLCICP
)zHM(

1etoN

000076.6633.33

100000.00133.33

010003.00134.33

110033.33133.33

001000.50100.53

101073.33143.33

011000.73152.43

111000.5705.73

000100.00133.33

100100.5976.13

010100.7933.23

110133.33133.33

001100.0900.03

101122.6970.23

011128.6614.33

111105.1905.03

3tiB

erawdrahybdetceleseramurtcepSdaerpSdnaycneuqerF-0

stupnidehctal,tceles

simurtcepSdaerpS;]4:6,2[tiBybdetcelessiycneuqerF-1

1tibybdetceles

0

1tiB

lamroN-0

delbanEmurtcepSdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

4

ICS9248-143

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB71 )tcanI/tcA(F_KLCICP

6tiB811 )tcanI/tcA(6KLCICP

5tiB711 )tcanI/tcA(5KLCICP

4tiB311 )tcanI/tcA(4KLCICP

3tiB211 )tcanI/tcA(3KLCICP

2tiB111 )tcanI/tcA(2KLCICP

1tiB011 )tcanI/tcA(1KLCICP

0tiB81 )tcanI/tcA(0KLCICP

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB641 )tcanI/tcA(F_KLCUPC
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB931 )tcanI/tcA(F_MARDS
2tiB241 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB541 )tcanI/tcA(0KLCUPC

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB821 )evitcanI/evitcA(7MARDS
2tiB921 )evitcanI/evitcA(6MARDS
1tiB131 )evitcanI/evitcA(5MARDS
0tiB231 )evitcanI/evitcA(4MARDS

5

ICS9248-143

Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-X #)84_42LES(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #3SFdehctaL
0tiB-1 )devreseR(

tiB#niPDWPnoitpircseD

7tiB431 )tcanI/tcA(3MARDS
6tiB531 )tcanI/tcA(2MARDS
5tiB731 )tcanI/tcA(1MARDS
4tiB831 )tcanI/tcA(0MARDS
3tiB621 )tcanI/tcA(zHM84
2tiB521 )tcanI/tcA(zHM42
1tiB841 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER