ICST AV9248F-138, ICS9248F-138 Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-138

Third party brands and names are the property of their respective owners.

Block Diagram

9248- 138 Rev A 10/03/00

Recommended Application:

810/810E and Solano type chipset.

Output Features:

• 2- CPUs @ 2.5V

• 9 - SDRAM @ 3.3V, including 1 free running

• 7 - PCICLK @ 3.3V

• 1 - IOAPIC @ 2.5V,

• 3 - 3V66MHz @ 3.3V

• 2 - 48MHz, @ 3.3V fixed.

• 1 - 24/48MHz, @3.3V selectable by I

2

C

• 1 - REF @v3.3V, 14.318MHz.

Features:

• Up to 200MHz frequency support

• Support FS0-FS4 strapping status bit for I

2

C read back.

• Support power management: Through Power down
Mode from I

2

C programming.

• Spread spectrum for EMI control ( ± 0.25% center).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• SDRAM - SDRAM: < 250ps

• 3V66 – 3V66: <175ps

• PCI – PCI: <500ps

• For group skew specifications, please refer to group
timing relationship.

Functionality

Pin Configuration

48-Pin 300mil SSOP

* These inputs have a 120K pull up to VDD.
** These inputs have a 120K pull down to GND.
1 These are double strength.

1

1

1

*SEL24_48#/REF0

VDDREF

X1
X2

GNDREF

GND3V66

3V66-0
3V66-1
3V66-2

VDD3V66

VDDPCI

*FS0/PCICLK0

**FS1/PCICLK1

GNDPCI
PCICLK2
PCICLK3
PCICLK4

VDDPCI
PCICLK5
PCICLK6

GNDPCI

PD#

SCLK

SDATA

VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
24_48MHz/FS2**
48MHz/FS3*
48MHz/FS4*
VDD48

1

1

ICS9248-138

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

SEL24_48#

PLL2

PLL1

Spread

Spectrum

48MHz [1:0]
24_48MHz

CPUCLK [1:0]

2

3

2

8

7

SDRAM [7:0]

IOAPIC

PCICLK [6:0]

SDRAM_F

3V66 [2:0]

X1

X2

XTAL
OSC

CPU

DIVDER

SDRAM
DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

SDATA

SCLK

FS[4:0]

PD#

Control

Logic

Config.

Reg.

/ 2

REF0

Frequency Generator & Integrated Buffers for Celeron & PII/III™

Additional frequencies selectable through I2C programming.

4SF3SF2SF1SF0SF

UPC

)zHM(

MARDS

)zHM(

66V3

)zHM(

KLCICP
)zHM(

CIPAOI

)zHM(
00000 76.6600.00176.6633.3376.61
00001 78.6603.00178.6634.3327.61
00010 76.8600.30176.8633.4361.71
00011 43.1700.70143.1766.5338.71
00100 00.00100.00176.6633.3376.61
00101 03.00103.00178.6634.3327.61
00110 00.30100.30176.8633.4371.71
00111 00.70100.70143.1766.5348.71
01000 33.33133.33176.6633.3376.61
0100 1 37.33137.33178.6634.3327.61
01010 33.73133.73176.8633.4371.71
01011 00.02100.02100.0600.0300.51
01100 33.33100.00176.6633.3376.61
01101 37.33103.00178.6634.3327.61
01110 33.73100.30176.8633.4371.71
01111 00.02100.0900.0600.0300.51

11010 00.06100.06100.0800.0400.02
1110 1 00.06100.02100.0800.0400.02
11011 76.66176.66143.3876.1448.02
11110 76.66100.52143.3876.1448.02

Preliminary Product Preview

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

2

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

General Description

Pin Configuration

The ICS9248-138 is the single chip clock solution for designs using the 810/810E and Solano style chipset. It provides all
necessary clock signals for such a system.

Spread spectrum may be enabled through I

2

C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-138 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I

2

C interface allows changing functions, stop clock programming and frequency selection.

PIN NUMBER PIN NAME TYPE DESCRIPTION

SEL2 4_ 4 8 MHz# IN

Logic inputs frequency select I/O /US B output,
When a "0" is latched, output frequency = 48MHz
Wh en a "1 " is latched, ou t

p

ut frequency = 24MHz

REF0 OUT 14.318 MHz reference clock.

2, 10, 1 1 , 18 , 2 5,

30, 38

VDD PWR

3.3V P o wer supply for SDR A M output buffers, PCI output buffers,
reference out

p

ut buffers and 48M Hz output
3 X1 IN Crystal input,nominally 14.318MHz.
4 X2 OUT Crystal output, nominally 14 .318 MHz.

5, 6, 14, 21, 29, 34,

42

GND P W R Gro und pin for 3V outputs.

9, 8, 7 3V66 [2:0] OU T 3.3V C locks

FS0 IN Frequency s e lect p in .

PCICLK0 OUT PCI clock output

FS1 IN Frequency s e lect p in .

PCICLK1 OUT PCI clock output

20, 19, 17, 16, 15 PCICLK [6:2] OUT P C I clock outputs.

22

PD# IN

Async hrono us active low input pin used to power down the devi c e into a low
po wer state. The internal clocks ar e disabled and the VCO and th e crys tal ar e
stopped. The latency of the pow er dow n will not be greater than 3ms.

23

SCLK IN Clock input of I2C input, 5V tolerant input

24

SDATA IN Data input for I2C serial input, 5V tolerant input

FS4 IN Frequency s e lect p in .

48MH z OUT 48MHz output clocks

FS3 IN Frequency s e lect p in .

48MH z OUT 48MHz output clocks

FS2

IN Frequency select pin.

24_48MHz OUT 24 or 48MHz output

31 SDRA M _F OUT

Free running SDRAM - used for feed back to chipset, should remain on
alwa

y

s.

32, 33, 35, 36, 37,

39, 40, 41,

SD R AM [7:0] OU T SD R AM clock outputs

43 GNDLCPU PWR Ground pin for the CPU clocks.

44, 45 CPUC LK [1:0] OUT C P U clock outputs.

46 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V
47 IOA P IC OUT 2.5V clock output

1

26

28

12

13

27

3

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

I2C is a trademark of Philips Corporation

tiBnoitpircseDDWP

tiB

4:7,2

2tib7tib6tib5tib4tib

KLCUPC

)zHM(

MARDS

)zHM(

66V3

)zHM(

KLCICP
)zHM(

CIPAOI

)HM(

egatnecerPdaerpS

0000,0

4SF3SF2SF1SF0SF
00000 76.6600.00176.6633.3376.61daerpSnwoD%5.0-ot0
0000 1 78.6603.00178.6634.3327.61daerpSretneC%52.0±
00010 76.8600.30176.8633.4361.71daerpSretneC%52.0±
00011 43.1700.70143.1776.5338.71daerpSretneC%52.0±
00100 00.00100.00176.6633.3376.61daerpSnwoD%5.0-ot0
00101 03.00103.00178.6634.3327.61daerpSretneC%52.0±
00110 00.30100.30176.8633.4371.71daerpSretneC%52.0±
00111 00.70100.70143.1776.5348.71daerpSretneC%52.0±
01000 33.33133.33176.6633.3376.61daerpSnwoD%5.0-ot0
01001 37.33137.33178.6634.3327.61daerpSretneC%52.0±
01010 33.73133.73176.8633.4371.71daerpSretneC%52.0±
01011 00.02100.02100.0600.0300.51daerpSretneC%52.0±
01100 33.33100.00176.6633.3376.61daerpSnwoD%5.0-ot0
01101 37.33103.00178.6634.3327.61daerpSretneC%52.0±
01110 33.73100.30176.8633.4371.71daerpSretneC%52.0±
01111 00.02100.0900.0600.0300.51daerpSretneC%52.0±

10000 00.63100.63100.8600.4300.71daerpSretneC%52.0±
1000 1 00.04100.04100.0700.5305.71daerpSretneC%52.0±
10010 76.24176.24143.1776.5348.71daerpSretneC%52.0±
1001 1 33.54133.54176.2733.6371.81daerpSretneC%52.0±
10100 00.63100.20100.8600.4300.71daerpSretneC%52.0±
1010 1 00.04100.50100.0700.5305.71daerpSretneC%52.0±
10110 76.24100.70143.1776.5348.71daerpSretneC%52.0±
1011 1 33.54100.90176.2733.6371.81daerpSretneC%52.0±
11000 76.64176.64143.3776.6343.81daerpSretneC%52.0±
1100 1 33.35133.35176.6733.8371.91daerpSretneC%52.0±
11010 00.06100.06100.0800.0400.02daerpSretneC%52.0±
11011 76.66176.66143.3876.1448.02daerpSretneC%52.0±
11100 76.64100.01143.3776.6343.81daerpSretneC%52.0±
11101 00.06100.02100.0800.0400.02daerpSretneC%52.0±
11110 76.66100.52143.3876.1448.02daerpSretneC%52.0±
11111 00.00200.00276.6633.3376.61daerpSretneC%52.0±

3tiB

stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0

4:6,2tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

daerpSretneC%52.0±delbanEmurtcepSdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

4

ICS9248-138

Preliminary Product Preview

Third party brands and names are the property of their respective owners.

Byte 1: SDRAM Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X#2SF
6tiB-X#1SF
5tiB131 F_MARDS
4tiB231 7MARDS

3tiB331 6MARDS

2tiB531 5MARDS

1tiB631 4MARDS

0tiB731 3MARDS

Byte 4: Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1 devreseR
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB-1 devreseR
2tiB621 0-zHM84
1tiB721 1-zHM84
0tiB821 zHM84_42

Byte 3: 3V66, Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X#4SF
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-X#3SF
3tiB-1 devreseR
2tiB71 0-66V3
1tiB81 1-66V3
0tiB91 2-66V3

Byte 2: PCI, Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1#0SF
6tiB021 6KLCICP

5tiB911 5KLCICP

4tiB711 4KLCICP

3tiB611 3KLCICP

2tiB511 2KLCICP

1tiB311 1KLCICP

0tiB211 0KLCICP

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.

Byte 5: Control Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X #84_42LES

6tiB110FER

5tiB741 CIPAOI

4tiB441 1KLCUPC

3tiB541 0KLCUPC

2tiB931 2MARDS

1tiB041 1MARDS

0tiB141 0MARDS

TIB#NIPDWPNOITPIRCSED

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

Byte 6: Control Register
(1= enable, 0 = disable)

Note: Dont write into this register, writing into this

register can cause malfunction