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ICS9248F-112
Datasheet
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ICST AV9248F-112, ICS9248F-112 Datasheet

Integrated Circuit Systems, Inc.
ICS9248-112
Third party brands and names are the property of their respective owners.
Block Diagram
9248- 112 Rev A 2/7/00
Recommended Application:
Output Features:
• 2- CPUs @2.5V, up to 150MHz.
• 9 - SDRAM @ 3.3V, up to150MHz including 1 free running
• 8 - PCICLK @ 3.3V
• 1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz
• 2 - 3V66MHz @ 3.3V, 2X PCI MHz
• 1- 48MHz, @3.3V fixed.
• 1- 24MHz, @3.3V fixed
• 1- REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support FS0-FS3 strapping status bit for I
2
C read back.
• Support power management: Through Power down Mode from I
2
C programming.
• Spread spectrum for EMI control ( ± 0.25% center).
• Spread can be enabled or disabled to all 32 frequencies throuth I
2
C.
• Uses external 14.318MHz crystal
Skew Specifications:
• CPU – CPU: <175ps
• SDRAM - SDRAM: < 250ps
• 3V66 – 3V66: <175ps
• PCI – PCI: <500ps
• CPU-SDRAM<500ps
• For group skew specifications, please refer to group timing relationship.
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD. 1 These are double strength.
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Additional frequencies selectable through I2C programming.
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0000 08.6602.00108.6604.3307.6104.33 0001 00.8600.20100.8600.4300.7100.43 0010 03.00103.00178.6634.3327.6134.33 0011 00.30100.30176.8633.4371.7133.43 0100 37.33103.00178.6634.3327.6134.33 0101 00.54157.80105.2752.6331.8152.63 0110 37.33103.00178.6634.3327.6134.33 0111 33.73100.30176.8633.4371.7133.43 100 0 00.04100.50100.0700.5305.7100.53 100 1 00.04100.04133.3976.6433.3276.64 1010 00.81100.81176.8733.9376.9133.93 101 1 00.42100.42176.2833.1476.0233.14 1100 07.33107.33131.9875.4482.2275.44 110 1 00.73100.73133.1976.5438.2276.54 1110 00.05105.21100.5705.7357.8105.73 1111 05.2757.80105.2752.6331.8152.63
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
Preliminary Product Preview
2
ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
Power Groups
GNDREF, VDDREF = REF0, X1, X2 GNDPCI , VDDPCI = PCICLK [9:0] GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F, supply for PLL core GND3V66 , VDD3V66 = 3V66 GND48 , VDD48 = 48MHz, 24_48MHz, VDDLAPIC = IOAPIC GNDLCPU , VDDLCPU = CPUCLK [1:0]
The ICS9248-112 is the single chip clock solution for designs using the 810/810E style chipset. It provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-112 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
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ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
 Controller (host) sends a start bit.  Controller (host) sends the write address D2
(H)
 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)
through byte 5
 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit
How to Read:
 Controller (host) will send start bit.  Controller (host) sends the read address D3
(H)
 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
H
ow to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
H
ow to Write:
4
ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. * These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread.
I2C is a trademark of Philips Corporation
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