ICST ICS9248F-103 Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9248-103

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

9248-103 Rev C 10/14/99

Pin Configuration

48-Pin SSOP

* Internal Pull-up Resistor of 120K to VDD

The ICS9248-103 is the single chip clock solution for Notebook designs using the 440BX or the VIA Apollo Pro 133 style chipset. It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-103 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

 Up to 137MHz frequency support  Spread Spectrum for EMI control  Serial I

C interface for Power Management,

Frequency Select, Spread Spectrum

 Provides the following system clocks

- 4-CPUs @ 2.5/3.3V, up to 137MHz (including CPUCLK_F)

- 9-SDRAMs @3.3V, up to 137MHz (including SDRAM_F)

- 8-PCI @3.3V, CPU/2 or CPU/3 (including 3 free running PCICLK_Fs)

- 1-24/48MHz @3.3V

- 1-48MHz @3.3V fixed

- 2-REF @3.3V, 14.318MHz.

 Efficient Power management scheme through PCI

and STOP CLOCKS

 Spread Spectrum ± .25%, & 0 to -0.5% down spread

Power Groups

VDDLCPU, GNDLCPU = CPUCLK [2:0], CPUCLK_F VDDSDR, GNDSDR = SDRAMCLKS [7:0], SDRAM_F VDDPCI, GNDPCI = PCICLKS [6:0], PCICLK_F VDD48, GND48 = 48MHz, 24MHz VDDREF, GNDREF = REF, X1, X2 VDDCOR = PLL CORE

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9248-103

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

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ICS9248-103

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.  Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

ACK

Byte 2

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

ICS9248-103

Functionality

VDD = 3.3V±5%, V

DDL

= 2.5V±5% or 3.3±5%, TA=0 to 70°C

Crystal (X1, X2) = 14.31818MHz

3SF2SF1SF0SF

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1000 00.00133.33 1001 00.5976.13 1010 13.3877.72 1011 33.33133.33 1100 00.0900.03 1101 22.6970.23 1110 28.6614.33 1111 5.195.03

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

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Note 1, Default at Power-up will be for

latched logic inputs to define frequency. Bit [2, 6:4] are default to 0010.

Note 2, PWD = Power-Up Default Note 3, When disabling spread spectrum

bit7 needs to be set to 0 to maintain nominal frequency.

ICS9248-103

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

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Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

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Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

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