ICST ICS9147F-12 Datasheet
Integrated
Circuit
Systems, Inc.
Pentium/ProTM System and Cyrix Clock Chip
General Description Features
The ICS9147-12 is a Clock Synthesizer chip for Pentium and
PentiumPro plus Cyrix CPU based Desktop/Notebook systems
that will provide all necessary clock timing.
Features include four CPU, seven PCI and eight SDRAM
clocks. Three reference outputs are available equal to the
crystal frequency, plus the IOAPIC output powered by VDDL.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30 pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF clock outputs
typically provide better than 0.5V/ns slew rates.
The ICS9147-12 accepts a 14.318MHz reference crystal or
clock as its input and runs on a 3.3V supply.
Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, plus 14.318 MHz REF(0:2), USB, Plus Super I/O
Supports single or dual processor systems
Supports Intel 60, 66.8MHz, Cyrix 55, 75MHz plus 83.3
and 68MHz (Turbo of 66.6) speeds.
Synchronous clocks skew matched to 250ps window on
CPU, SDRAM and 500ps window on PCI clocks
CPU clocks to PCI clocks skew 1-4ns (CPU early)
Two fixed outputs, 48MHz and 24 MHz
Separate 2.5V and 3.3V supply pins
- 2.5V or 3.3V output: CPU, IOAPIC
- 3.3V outputs: SDRAM, PCI, REF, 48/24 MHz
No power supply sequence requirements
48 pin 300 mil SSOP
ICS9147-12
Block Diagram
Pin Configuration
48-Pin SSOP
Power Groups
VDD1 = REF (0:2), X1, X2
VDD2 = PCICLK_F, PCICLK (0:5)
VDD3 = SDRAM (0:7),
VDD4 = 48MHz, 24MHz
VDDL = IOAPIC, CPUCLK (0:3)
9147-12 Rev A 072597P
Pentium is a trademark on Intel Corporation.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
Pin Descriptions
PIN NUMBER PIN NAME TYPE DESCRIPTION
1
2 REF0 OUT Reference clock output
3, 10, 17, 24, 31,
31, 37, 43
4X1 IN
5 X2 OUT Crystal output, includes internal load cap to GND.
6, 20, N/C - Pins are not internally connected
7, 15 VDD2 PWR Supply for PCICLK_F, and PCICLK (0:5)
8 PCICLK_F OUT Free running PCI clock
9, 11, 12, 13, 14, 16 PCICLK (0:5) OUT PCI clocks
18 FS0 IN Frequenc y select 0 inpu t
19 FS1 IN Frequenc y select 1 inpu t
21 VDD4 PWR Supply for 48MHz and 24MHz clocks
22 48MHz OUT 48MHz driver output for USB clock
23 24MHz OUT 24MHz driver output for Super I/O clock
25, 28,34 VDD3 PWR Supply for SDRAM (0:7),
26, 27, 29, 30,
32, 33, 35, 36
38, 39, 41, 42 CPUCLK (0:3) OUT CPUCLK clock output, powered by VDDL
40, 46 VDDL PWR Supply for CPUCLK (0:3) & IOAPIC
44 PD# IN
45 IOAPIC OUT IOAPIC clock output, powered by VDDL at crystal frequency
47 REF2 OUT Ref erence clock outpu t.
48 VDD1 PWR Supply for REF (0:2), X1, X2
FS2 IN Latched input for frequency select2
REF1 OUT Reference clock output
GND PWR Ground (common)
Crystal or refer ence input, nomi nally 14.318 M Hz. Includes
internal load cap to GND and fee dback resistor from X2.
1
1
SDRAM (0:7) OUT SDRAMs clock at CPU sp eed
Power down stops all clocks low and d isables oscillator and
internal VCO’s.
2
ICS9147-12
1
Note 1: Internal pull-up resistor of nomimally 100K to 120K at 3.3V on indicated inputs.
Note 2: The PD# input pin has a protection diode clamp to the VDDL power supply. If VDDL is not connected to VDD, (ie
VDDL=2.5V, VDD=3.3V) then this input must have a series resistor if the logic high is connected to VDD. This input
series resistor provides current limit for the clamp diode. For a pullup to VDD it should be 1Kohm or more from the PD#
pin to VDD. If the PD# pin is being driven by logic powered by 3.3V, then a 100Ω series resistor will be suffcient.
2
Functionality
VDD = 3.3V ±5%, V
Crystal (X1, X2) = 14.31818 MHz
= 2.5V ±5% or 3.3V ±5%, TA = 0 to 70°C
DDL
ICS9147-12
FS2 FS1 FS0
0 0 0 83.3 1/2 CPU
0 0 1 75 30
0 1 0 83.3 33.3
0 1 1 68.5 1/2 CPU
1 0 0 55 1/2 CPU
1 0 1 75 1/2 CPU
1 1 0 60 1/2 CPU
1 1 1 66.8 1/2 CPU
CPUCLK, SDRAM
(MHz)
Power Management Functionality
PD#
0 Stopped Low Stopped Low Stopped Low Off Off
1 Running Running Running Running Running
CPUCLK
Outputs
PCICLK(0:5)
Outputs
PCICLK_ F,
REF,
24/48MHz
and SDRAM
PCICLK
(MHz)
Crystal
OSC
VCO
3
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