ICST GSP90C65V, GSP90C65N, GSP90C65M, AV90C65V, AV90C65N Datasheet

90C65ARevA111095

Dual Volta ge Video/ Memory Clock Gener ator

Introduction

The Integrated Circuit Systems ICS90C65 is a dual clock
generator for VGA applications. It simultaneously generates
two clocks. One clock is for the video memory, and the other
is the vide o dot clock.

The ICS90C65 has been specifically designed to serve the
por ta b le PC market with operation at ei ther 3.3 V o r 5V with a
comprehe nsiv e power - savi ng shut -do wn mode .

This data sheet supplies sales order information, a functional
overview, signal pin details, a block diagram, AC/DC charac­teristics, timing diagrams, and package mechanical information.

Description

The Integrated Circuit Systems Video Graphics Array Clock
Generator (ICS90C65) is capable of producing different out­put frequencies under firmware control. The video output
frequency is derived from a 14.318 MHz system clock avail­able in IBM PC/XT/AT and Personal System/2 computers. It
is designed to work with Western Digital Imaging Vi deo
Graphics Array and 8514/A devices to optimize vi deo subsys­tem performance.

Features

•• Specified for dual voltage operation (VDD=3.3V or 5V),

but operates c ont inu ously from 3.0V to 5.25 V

•• Designed t o be powe re d-do wn for e xten de d ba tter y life

•• Backwa rd c ompa ti bilit y to the ICS90 C64 a nd IC S90C6 3

•• Dual Clock generator for the IBM-compatible Western

Digital Imagin g Vide o Gra ph ics Arra y (VGA) LSI
devices, an d 8514/A chip sets

•• Integral loop filter components, reduce cost and phase

jitt er

•• Generates fifteen video clock frequencies (including

25.175 and 28.322 MHz) derived from a 14.318 MHz
system cloc k reference frequency

•• On-chip ge ne ra tion of ei ght mem ory clo ck fre que nc ie s

•• Video clo ck is s el ectab le amo ng t he 15 in te rnal ly gene r-

ated clocks and one external clock

•• CMOS technology

•• Available in 20-pi n PL CC, SOIC and DIP pa c kage s

Integrated
Circuit
Systems, Inc.

Note:ICS90C65N (DIP) pin-out is identical to ICS90C65M (SOIC) pin-out.

ICS90C 65

The video dot clock output may be one of 15 internally­gener at ed fr eq uen cies or one exte rn al inpu t. T he selec ti on of
the video dot cloc k fre qu en cy is done through four inputs.

•• VSEL0

•• VSEL1

•• VSEL2

•• VSEL3

VSEL0 an d V SEL1 are lat c hed by the SEL EN signal. VS E L 2
and VSEL3 are used as direct inputs to the VCLK selection.
Table 1-1 is the truth table for VCLK selection.

The input a nd tr uth ta ble ha ve be en desi gned to allow a dire ct
connecti on t o one of th e ma ny Weste rn Digital Imagi ng V G A
controlle rs or 851 4/A chip sets.

The MCL K output is one of eight intern ally-ge nerate d frequ en­cies as shown in Table 1-2. The various VCLK and MCLK
frequen cies a re deri ved from the 14. 318 MHz in put fre quenc y .

The VCLKE and MCLKE input can tristate the VCLK and
MCLK output s to fa cili ta t e boar d le ve l test ing.

ICS90C65 VGA Interface

The ICS90C65 has two system interfaces: System Bus and
VGA Controll er, as well as othe r programm able in puts. Figure
1 shows how the Integrated Circuit Systems’s VGA Clock
ICS90C65 is connected to a VGA controller. Western Digital
Imaging VGA controllers normally have a status bit that indi­cates to the VGA cont roller that it is working with a cloc k chip.
When working with a clock chip the VGA controller changes
two of its clock inputs to outputs. They are
theVCLK1/VCSLD/VCSEL and VCLK2/VCSEL/VCSELH
outputs and they are used to select the required video frequency.

Figure 1

When the power-down capab ilit ies a re used, the co ntr ol sign al
for

PWRDN is normally held in one of a group of latches. If

the power-down function is not to be used, PWRDN must be

tied to VDD, other wise the i nternal pull-do wn will p lace the chip

in the power-down mode.

VSEL0

14.318
MHz

SD3

SD2

pull-up at reset
and PR15(5)=0

AMD(3)

VCKIN
MCLK

VCSEL

VCS

ICS90C65

WD90C26

LATCH

VSEL1
VSEL2

VCLK

MC

SELEN
CLK1

PWRDN

ICS90C65

2

Inputs from VGA Controller

The VGA controll e r inp ut t o t he ICS90C65 is:

•• SELEN

The ICS90C65 is programmed to generate different video
clock frequ encies using t he inputs of VSEL 0, VSEL1, VSE L2,
and VSEL3. The sig nals VSE L2 and VSEL 3 ma y be supplie d
by the V GA c ontroll er as is the case in W estern Digital Imagin g
VGA contr ollers. T he inputs VSEL0-1 ar e latched w ith the
signal SELEN. The SELEN input should be an active low
puls e. Thi s act ive l ow pu lse is gene rated in Western Digi tal
Imagin g VG A co ntr oll ers during I/ O wri te s to in terna l regi st er
3C2h.

Note: Only VSEL 0 and VSEL1 are latched with signal SELEN.

Outputs to VGA Controller

The outputs from th e ICS90C65 to the VGA controller are:

•• MCLK

•• VCLK

MCLK and VCLK are the two clock outputs to the VGA
controller.

User-Definable Inputs

The user de fi nable inputs are :

•• EXTCLK

•• VLCKE, MCLKE

•• MSELO-2

•• VSEL2, VSEL3

••

PWRDN

EXTCLK is an additional input that may be internally routed
to the VCLK o utput. This addi tional input is useful for supp ort­ing modes that require frequencies not provided by the
ICS90C65 or for use during bo ar d test.

VCLKE and MCLKE a re the outpu t enable signals for VCL K
and MCLK. When low the re sp e ct iv e o utp ut i s tri sta te d.

MSEL0-2 are the memory clock (M CLK) select lines. Ta­ble 1-2 shows how MCLK frequencie s are selected. All signals
in this group ha ve internal pull-up resistors.

VSEL2 and VSEL3 are video clock (VCLK) select lines that
can select add it ion al VCL K fre qu en ci es. Se e Table 1-1.

VSEL2 and VSE L3 have internal pull-ups.
PWRDN can place the ICS90C65 in a power-down mode

which drops its suppl y current requirem ent below 1 microam p.
When placed in this mode, the digital inputs may be either high
or low or f loating withou t causing an inc rease in the ICS90C65
supply current .

The

PWRDN pin must be low (It has an internal pull-down.)

in order to place the device in its low power state. The output
pins (VCLK and MCLK) are driven high by the ICS90C65
when it is in its low power state .

If CLKI is being driven by an external source, it may be driven
low or high without a power penalty. If CLKI is at an interm e­diate vo lt ag e ( V

SS

+0.5 < V

IN <VDD

-0.5) , the re wi ll be a sm all

increase in supply current. If CLKI is driven at 14.318 MHz
while the c hip is i n power -down, the ICS90C65 supp ly curre nt
will incre ase to appr oxi mat el y 1.2 mA.

The SELEN (pin 6) may be used to guard against inadvertent
frequency changes during power-down/powerup sequences.
By holding the SELEN low du ring powe r -down and powe r-u p
sequences, the ICS90C65 will retain the most recent video
frequency selection.

Analog Filters

The an alog fi lters ar e integral to the ICS90C65 device. No
external components are required. This feature reduces PC
board space re quire me nts and com ponent costs. Pha se -jitt er is
reduced as externally-generated noise cannot easily influence
the phase -locked loo p filter .

System Bus Inputs

The system bus inputs are:

•• CLKI

•• VSEL0

•• VSEL1

The ICS90C65 uses the system bus 14.318 MHz clock as a
reference to generate all its frequencies for both video and
memory clo cks. Data lines D2 and D3 are commonly used as
inputs to VSEL0 and VSE L 1 for vi de o frequ en cy selec t ion .

ICS90C65

3