ICST ICS8737AG-11, ICS8737AG-11T Datasheet

Integrated
Circuit
Systems, Inc.

ICS8737-11

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÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

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1/

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2

GENERAL DESCRIPTION

,&6

HiPerClockS™

inputs. The CLK, nCLK pair can accept most standard differ­ential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels.The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.

Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.

The ICS8737-11 is a low skew, high performance
Differential-to-3.3V LVPECL Clock Generator/
Divider and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8737-11 has two selectable clock

FEATURES

• 2 divide by 1 differential 3.3V L VPECL outputs;
2 divide by 2 differential 3.3V L VPECL outputs

• Selectable CLK, nCLK or LVPECL clock inputs

• CLK, nCLK pair can accept the following differential input

levels: L VDS, L VPECL, LVHSTL, SSTL, HCSL

• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL

• Maximum output frequency up to 650MHz

• Translates any single ended input signal (L VCMOS, L VTTL,

GTL) to LVPECL levels with resistor bias on nCLK input

• Output skew: 60ps (maximum)

• Part-to-part skew: 200ps (maximum)

• Bank skew: Bank A - 20ps (maximum),

Bank B - 35ps (maximum)

• Propagation delay: 1.7ns (maximum)

• 3.3V operating supply

• 0°C to 70°C ambient operating temperature

• Industrial temperature information available upon request

BLOCK DIAGRAM PIN ASSIGNMENT

CLK_EN

CLK
nCLK
PCLK

nPCLK

CLK_SEL

MR

QA0
nQA0

D

Q

LE

0
1

÷1
÷2

QA1
nQA1

QB0
nQB0

QB1
nQB1

VEE

CLK_EN

CLK_SEL

CLK
nCLK
PCLK

nPCLK

nc
MR
V

CC

ICS8737-11

20-Lead TSSOP

1
2
3
4
5
6
7
8
9
10

6.50mm x 4.40mm x 0.92 package body

G Package

T op View

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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20
19
18
17
16
15
14
13
12
11

QA0
nQA0
V

CC

QA1
nQA1
QB0
nQB0
V

CC

QB1
nQB1

Integrated
Circuit
Systems, Inc.

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

1V

2NE_KLCrewoPpulluP

3LES_KLCtupnInwodlluP
4KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN

5KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
6KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN
7KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
8cndesunU.tcennocoN
9RMtupnInwodlluP.redividtuptuoehtsteseR.teserretsaM

81,31,01V
21,111BQ,1BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
51,410BQ,0BQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
71,611AQ,1AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD
02,910AQ,0AQntuptuO.slevelecafretniLCEPVL.riaptuptuolaitnereffiD

:ETON

EE

CC

pulluP

dna

rewoP.dnuorgottcennoC.nipylppusevitageN

rewoP.V3.3ottcennoC.snipylppusevitisoP

nwodlluP

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

.slevelecafretniSOMCVL/LTTVL

.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleSkcolC

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

÷

1/

÷÷

.tupnikcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS

2

.slevelecafretniSOMCVL/LTTVL.stupniKLCn,KLCstceles,WOLnehW

÷÷

.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW

TABLE 2. PIN CHARACTERISTICS

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

C

NI

R

PULLUP

R

NWODLLUP

ecnaticapaCtupnI

KLCn,KLC 4Fp

KLCPn,KLCP 4Fp

,LES_KLC

RM,NE_KLC

rotsiseRpulluPtupnI 15K

rotsiseRnwodlluPtupnI 15K

4Fp

W
W

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

2

Integrated
Circuit
Systems, Inc.

ICS8737-11

LOW SKEW

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERAT OR

TABLE 3A. CONTROL INPUT FUNCTION TABLE

stupnIstuptuO

RMNE_KLCLES_KLCecruoSdetceleS1AQurht0AQ1AQnurht0AQn1BQurht0BQ1BQnurht0BQn

1X X X WOLHGIHWOLHGIH
00 0 KLCn,KLCWOL;delbasiDHGIH;delbasiDWOL;delbasiDHGIH;delbasiD
00 1 KLCPn,KLCPWOL;delbasiDHGIH;delbasiDWOL;delbasiDHGIH;delbasiD
01 0 KLCn,KLCdelbanEdelbanEdelbanEdelbanE
01 1 KLCPn,KLCPdelbanEdelbanEdelbanEdelbanE

.1erugiFfinwohssa

.B3elbaTni

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÷

÷

1/

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2

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egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA

debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQA0 - nQA1,

nQB0 - nQB1

QA0 - QA1,

QB0 - QB1

TABLE 3B. CLOCK INPUT FUNCTION TABLE

stupnIstuptuO

KLCProKLCKLCPnroKLCnxAQxAQnxBQxBQn

00WOLHGIHWOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
11HGIHWOLHGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN
01ETON;desaiBWOLHGIHWOLHGIHlaitnereffiDotdednEelgniSgnitrevnInoN
11ETON;desaiBHGIHWOLHGIHWOLlaitnereffiDotdednEelgniSgnitrevnInoN

1ETON;desaiB0HGIHWOLHGIHWOLlaitnereffiDotdednEelgniSgnitrevnI
1ETON;desaiB1WOLHGIHWOLHGIHlaitnereffiDotdednEelgniSgnitrevnI

.sleveldedneelgnistpecca

Disabled

Enabled

FIGURE 1: CLK_EN TIMING DIAGRAM

edoMtuptuOottupnIytiraloP

ottupnilaitnereffidgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

3

Integrated
Circuit
Systems, Inc.

ICS8737-11

÷÷

÷÷

÷

LOW SKEW

÷÷

1/

÷

÷÷

2

DIFFERENTIAL-TO- 3.3V L VPECL CLOCK GENERA TOR

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

Inputs, V

I

Outputs, V

Package Thermal Impedance, θ

Storage T emperature, T

CC

O

JA

STG

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the

DC Characteristics

or

AC Characteristics

ods may affect product reliability .

4.6V

-0.5V to VCC + 0.5V

-0.5V to VCC + 0.5V

73.2°C/W (0lfpm)

-65°C to 150°C

is not implied. Exposure to absolute maximum rating conditions for extended peri-

TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V

= 3.3V±5%, TA = 0°C TO 70°C

CC

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

CC

I

EE

egatloVylppuSevitisoP531.33.3564.3V

tnerruCylppuSrewoP 05Am

TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

V

HI

V

LI

I

HI

I

LI

TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

I

HI

I

LI

V

PP

V

RMC

2,1ETON

RM,LES_KLC,NE_KLC2567.3V
RM,LES_KLC,NE_KLC 3.0-8.0V

tnerruChgiHtupnI

tnerruCwoLtupnI

tnerruChgiHtupnI

tnerruCwoLtupnI

NE_KLCV

RM,LES_KLCV

NE_KLCV

RM,LES_KLCV

= 3.3V±5%, TA = 0°C TO 70°C

CC

KLCnV

KLCV

KLCnV

KLCV

NI

NI

NI

NI

egatloVtupnIkaeP-ot-kaeP 51.03.1V

;egatloVtupnIedoMnommoC

snoitacilppadedneelgnisroF:1ETON , VsiKLCn,KLCrofegatlovtupnimumixameht

siegatlovedomnommoC:2ETONVsadenifed

.

= 3.3V±5%, TA = 0°C TO 70°C

CC

V=

NI

CC

V=

NI

CC

V,V0=

NI

V,V0=

NI

V=

CC

V=

CC

V,V0=

CC

V,V0=

CC

V564.3=5Aµ
V564.3=051Aµ

CC

CC

V564.3=051-Aµ
V564.3=5-Aµ

V564.3=5Aµ
V564.3=051Aµ

V564.3=051-Aµ
V564.3=5-Aµ

V

5.0+V

EE

CC

.V3.0+

CC

58.0-V

8737AG-11 www.icst.com/products/hiperclocks.html REV. A JULY 13, 2001

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