ICST ICS8702BY, ICS8702BYT Datasheet
Integrated
Circuit
Systems, Inc.
ICS8702
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
GENERAL DESCRIPTION
The ICS8702 is a very low skew, ÷1, ÷2 Clock
,&6
HiPerClockS™
els. True or inverting, single-ended to LVCMOS translation
can be achieved with a resistor bias on the nCLK or CLK
inputs, respectively. The effective fanout can be increased
from 20 to 40 by utilizing the ability of the outputs to drive two
series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, supports enabling and disabling each
bank of outputs individually. The master reset input, nMR/OE,
resets the internal frequency dividers and also controls the
enabling and disabling of all outputs simultaneously.
The ICS8702 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output, multiple frequency and part-to-part skew characteristics make the ICS8702 ideal for those clock distribution applications demanding well defined performance and
repeatability.
Generator and a member of the HiPerClockS
family of High Performance Clock Solutions
from ICS. The ICS8702 is designed to translate any differential signal levels to LVCMOS lev-
FE ATURES
20 LVCMOS outputs, 7Ω typical output impedance
Output frequency up to 250 MHz
150ps bank skew, 200ps output, 250ps multiple frequency
skew, 650ps part-to-part skew
Translates any differential input signal (PECL, HSTL, LVDS)
to LVCMOS levels without external bias networks
Translates any single-ended input signal to LVCMOS levels
with a resistor bias on nCLK input
Translates any single-ended input signal to inverted LVCMOS
levels with a resistor bias on CLK input
LVCMOS / LVTTL control inputs
Bank enable logic allows unused banks to be disabled
in reduced fanout applications
3.3V or mixed 3.3V input, 2.5V output operating
supply modes
48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
0°C to 70°C ambient operating temperature
Other divide values available on request
BLOCK DIAGRAM PIN ASSIGNMENT
GND
CLK
nCLK
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
÷1
÷1
÷2
÷2
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
Bank Enable
Bank Enable
Logic
Logic
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
GND
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
DIV_SELD
QC1
QC2
VDDI
nMR/OE
DIV_SELC
48-Lead LQFP
QC0
QB4
VDDO
VDDO
ICS8702
VDDI
BANK_EN0
GND
BANK_EN1
Y Package
Top View
QB3
nCLK
GND
QB2
DIV_SELB
CLK
GND
36
35
34
33
32
31
30
29
28
27
26
25
DIV_SELA
QB1
VDDO
QB0
QA4
VDD0
QA3
GND
QA2
GND
QA1
VDDO
QA0
8702 www.icst.com REV. A - AUGUST 7, 2000
1
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,62,11,5,2
44,14,53,23
,03,82,9,7
84,64,93,73
02,61IDDVrewoP.V3.3ottcennoC.ylppusrewoptupnI
81DNGrewoP.dnuorgottcennoC.ylppusrewoptupnI
,92,72,52
33,13
,83,63,43
24,04
,74,54,34
3,1
,8,6,4
21,01
22KLCtupnInwodlluP .slevellaitnereffidynastpeccA.tupnikcolclaitnereffidgnitrevni-noN
12KLCntupnIpulluP.slevellaitnereffidynastpeccA.tupnikcolclaitnereffidgnitrevnI
31DLES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoDknabrofnoisividycneuqerfslortnoC
41CLES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoCknabrofnoisividycneuqerfslortnoC
32BLES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoBknabrofnoisividycneuqerfslortnoC
42ALES_VIDtupnIpulluP .slevelecafretniSOMCVL.stuptuoAknabrofnoisividycneuqerfslortnoC
91,71
51EO/RMntupnIpulluP
ODDVrewoP.V5.2roV3.3ottcennoC.ylppusrewoptuptuO
DNGrewoP.dnuorgottcennoC.ylppusrewoptuptuO
ICS8702
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
,2AQ,1AQ,0AQ
4AQ,3AQ
,2BQ,1BQ,0BQ
4BQ,3BQ
,2CQ,1CQ,0CQ
4CQ,3CQ
,2DQ,1DQ,0DQ
4DQ,3DQ
,1NE_KNAB
0NE_KNAB
tuptuO7.stuptuoAknaB Ω .ecnadepmituptuolacipyt
tuptuO7.stuptuoBknaB Ω .ecnadepmituptuolacipyt
tuptuO7.stuptuoCknaB Ω .ecnadepmituptuolacipyt
tuptuO7.stuptuoDknaB Ω .ecnadepmituptuolacipyt
tupnIpulluP .slevelecafretniSOMCVL.sknabybstuptuoselbasiddnaselbanE
llaselbasiddnaselbanE.sredividkcolcsteseR.teserretsamsuonorhcnysA
.slevelecafretniSOMCVL.stuptuo
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
NICecnaticapaCtupnI Fp
PULLUPRrotsiseRpulluPtupnI 15KΩ
NWODLLUPRrotsiseRnwodlluPtupnI 15KΩ
DPCecnaticapaCnoitapissiDrewoP
)tuptuorep(
TUORecnadepmItuptuO 7
V564.3=ODDV,IDDV Fp
V526.2=ODDV,V564.3=IDDV Fp
TABLE 3A. CONTROL INPUTS FUNCTION TABLE
stupnI stuptuO
EO/RMn1NE_KNAB0NE_KNABxLES_VID4AQ-0AQ4BQ-0BQ4CQ-0CQ4DQ-0DQycneuqerfxQ
0X XX ZiHZiHZiHZiHorez
10 00 evitcAZiHZiHZiH2/NIf
11 00 evitcAevitcAZiHZiH2/NIf
10 10 evitcAevitcAevitcAZiH2/NIf
11 10 evitcAevitcAevitcAevitcA2/NIf
10 0 1 evitcAZiHZiHZiHNIf
11 01 evitcAevitcAZiHZiHNIf
10 11 evitcAevitcAevitcAZiHNIf
11 11 evitcAevitcAevitcAevitcANIf
Ω
8702 www.icst.com REV. A - AUGUST 7, 2000
2
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
LOCK GENERATOR
C
ICS8702
TABLE 3B . CLOCK INPUTS FUNCTION TABLE
stupnIstuptuO
EO/RMnKLCKLCn4xQurht0xQ
10 1 WOLdednEelgniSotlaitnereffiDgnitrevnInoN
110 HGIHdednEelgniSotlaitnereffiDgnitrevnInoN
10 1ETON;desaiBWOLdednEelgniSotdednEelgniSgnitrevnInoN
11 1ETON;desaiBHGIHdednEelgniSotdednEelgniSgnitrevnInoN
11ETON;desaiB0HGIHdednEelgniSotdednEelgniSgnitrevnI
11ETON;desaiB1WOLdednEelgniSotdednEelgniSgnitrevnI
1.0adnadnuorgµ .Vm003±2/DDVyletamixorppasitniophctiwsgnitluserehT.dnuorgottupniehtmorfroticapacF
edoMtuptuOottupnIytiraloP
roftniophctiwsehtstestupnidesaibehttaegatlovehT.desaibebstupnilaitnereffidehtfoenotahtseriuqeresutupnidedneelgniS:1ETON
oteulavlauqeforotsisera,IDDVotrotsiserasikrowtensaibtupnidednemmocerehtsleveltupniSOMCVLroF.tupnidedneelgniseht
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 4.6V
Inputs -0.5V to VDD + 0.5V
Outputs -0.5V to VDDO + 0.5V
Ambient Operating Temperature 0°C to 70°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Electrical
Characteristics or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
8702 www.icst.com REV. A - AUGUST 7, 2000
3
Integrated
Circuit
Systems, Inc.
LOW SKEW ¸1, ¸2
C
LOCK GENERATOR
ICS8702
TABLE 4A. DC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V
ODDVegatloVylppuSrewoPtuptuO 531.33.3564.3V
HIVegatloVhgiHtupnIKLCn,KLCtpecxellAV564.3=IDDV28.3V
LIVegatloVwoLtupnI;KLCn,KLCtpecxellAV531.3=IDDV3.0-8.0V
PPV
RMCV
HIItnerruChgiHtupnI
LIItnerruCwoLtupnI
DDItnerruCylppuSrewoPtnecseiuQ
HOVegatloVhgiHtuptuO
LOVegatloVwoLtuptuO
egatloV
.1erugiFeeS.egatlov
tupnIkaeP-ot-kaeP
tupnIedoMnommoC
1ETON;egatloV
KLCn,KLC51.03.1V
KLCn,KLC
KLCtpecxellAV564.3=NIV=IDDV5Aµ
KLCV564.3=NIV=IDDV051Aµ
KLCtpecxellAV0=NIV,564.3=IDDV051-Aµ
KLC0=NIV,564.3=IDDV5-Aµ
sleveLLCEPVL8.14.2V
sleveL
LTSS,SDVL,LTSH,MCD
V564.3=HIV=IDDV
V0=LIV
V531.3=ODDV=IDDV
Am63-=HOI
V531.3=ODDV=IDDV
Am63=LOI
13.03.1V
07Am
6.2V
5.0V
=ICCVroferaA4elbaTnidetonseulavLCEPVLehT.HIVmuminimehtsadenifedsiLCEPVLrofegatlovtupniedomnommoC:1ETON
revossorcehtsadenifedsiLTSSdnaSDVL,LTSH,MCDrofegatlovtupniedomnommoC.ICCVhtiw1:1yravlliwLCEPVLrofRMCV.V3.3
TABLE 5A. AC ELECTRICAL CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
XAMfycneuqerFtupnImumixaM 052zHM
HLpthgiH-ot-woL,yaleDnoitagaporPZHM0 < f ≤ zHM0022.25.3sn
LHptwoL-ot-hgiH,yaleDnoitagaporPZHM0 < f ≤ zHM0022.25.3sn
)b(kst2ETON;wekSknaB 2/ODDVtaegdegnisirnoderusaeM051sp
)o(kst3ETON;wekStuptuO 2/ODDVtaegdegnisirnoderusaeM002sp
(kst ω)4ETON;wekSycneuqerFelpitluM 2/ODDVtaegdegnisirnoderusaeM052sp
)pp(kst5ETON;wekStraPottraP 2/ODDVtaegdegnisirnoderusaeM056sp
Rt6ETON;emiTesiRtuptuO%07ot%03082058sp
Ft6ETON;emiTllaFtuptuO%07ot%03082058sp
WPthtdiWesluPtuptuO
NEtemiTelbanEtuptuO6ETON;zHM01=f6sn
SIDtemiTelbasiDtuptuO6ETON;zHM01=f6sn
ZHM0 < f < zHM002
zHM002=f25.23sn
.noitcudorpnidetsettoN.noitaziretcarahcybdeetnaraugerasretemarapesehT:6ETON
2/ELCYCt
5.0-
2/ELCYCt
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofoknabanihtiwwekssadenifeD:2ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttastuptuofosknabssorcawekssadenifeD:3ETON
2/ELCYCt
5.0+
05htiwdetanimretstuptuollA.esiwrehtodetonsselnuVm003=PPVdnazHM002=NIftaderusaemsretemarapllA:1ETON Ω .2/ODDVot
sn
.snoitidnocdaollauqednasegatlovylppusemasehthtiwycneuqerftnereffidtagnitarepostuptuofosknabssorcawekssadenifeD:4ETON
.snoitidnocdaollauqehtiwdnasegatlovylppusemasehttagnitareposecivedtnereffidnostuptuotnereffidtaweksehtsadenifeD:5ETON
8702 www.icst.com REV. A - AUGUST 7, 2000
4
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