ICST ICS8701CYI, ICS8701CYIT Datasheet
Integrated
Circuit
Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8701I is a low skew, ÷1, ÷2 Clock Gen-
,&6
HiPerClockS™
allel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS8701I is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics
make the ICS8701I ideal for those clock distribution applications demanding well defined performance and repeatability.
erator and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS outputs are designed to drive 50W series or par-
FEATURES
• 20 LVCMOS outputs, 7W typical output impedance
• Output frequency up to 250MHz
• 200ps bank skew, 250ps output skew, 300ps multiple
frequency skew, 600ps part-to-part skew
• LVCMOS / LVTTL clock input
• LVCMOS control inputs
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
• -40°C to 85°C ambient operating temperature
• Other divide values available on request
BLOCK DIAGRAM PIN ASSIGNMENT
GND
LVCMOS_CLK
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
¸
1
¸
2
1
0
1
0
1
0
1
0
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
Bank Enable
Logic
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
VDDO
QD4
GND
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23
24
DIV_SELD
QC1
QC2
ICS8701I
VDDI
nMR/OE
DIV_SELC
48-Pin LQFP
QC0
QB4
BANK_EN0
GND
VDDO
VDDI
VDDO
BANK_EN1
Y Package
Top View
GND
QB2
QB3
DIV_SELB
LVCMOS_CLK
GND
GND
36
35
34
33
32
31
30
29
28
27
26
25
DIV_SELA
QB1
VDDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
VDDO
QA0
8701I www.icst.com/products/hiperclocks.html REV. A MARCH 16, 2001
1
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,5,2
,62,11
,53,23
44,14
,81,9,7
,03,82,12
,64,93,73
84
02,61IDDVrewoP.V3.3ottcennoC.ylppusrewoptupnI
,72,52
,92
33,13
,63,43
,83
24,04
,54,34
,74
3,1
,6,4
,8
21,01
22KLC_SOMCVLtupnInwodlluP.slevelecafretniSOMCVL.tupnikcolC
31DLES_VIDtupnIpulluP
41CLES_VIDtupnIpulluP
32BLES_VIDtupnIpulluP
42ALES_VIDtupnIpulluP
91,71
51EO/RMntupnIpulluP
ODDVrewoP.V5.2roV3.3ottcennoC.ylppusrewoptuptuO
DNGrewoP.dnuorgottcennoC.dnuorG
,1AQ,0AQ
,2AQ
4AQ,3AQ
,1BQ,0BQ
,2BQ
4BQ,3BQ
,1CQ,0CQ
,2CQ
4CQ,3CQ
,1DQ,0DQ
,2DQ
4DQ,3DQ
,1NE_KNAB
0NE_KNAB
tuptuO
tuptuO
tuptuO
tuptuO
tupnIpulluP .slevelecafretniSOMCVL.sknabybstuptuoselbasiddnaselbanE
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
.slevelecafretniSOMCVL.stuptuoAknaB
7
W
7
W
7
W
7
W
.ecnadepmituptuolacipyt
.slevelecafretniSOMCVL.stuptuoBknaB
.ecnadepmituptuolacipyt
.slevelecafretniSOMCVL.stuptuoCknaB
.ecnadepmituptuolacipyt
slevelecafretniSOMCVL.stuptuoDknaB
.ecnadepmituptuolacipyt
.stuptuoDknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuoCknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuoBknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuoAknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
.stuptuollaselbasiddnaselbanE.elbanetuptuodnateserretsaM
.slevelecafretniSOMCVL
8701I www.icst.com/products/hiperclocks.html REV. A MARCH 16, 2001
2
Integrated
Circuit
Systems, Inc.
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
KLC_SOMCVL Fp
NIC
PULLUPRrotsiseRpulluPtupnI 15K
NWODLLUPRrotsiseRnwodlluPtupnI 15K
DPCecnaticapaCnoitapissiDrewoP
TUORecnadepmItuptuO 7
tupnI
ecnaticapaC
,1NE_KNAB
)tuptuorep(
TABLE 3. FUNCTION TABLE
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,EO/RMN,0NE_KNAB
=ODDV,IDDV
V564.3
,V564.3=IDDV
V526.2=ODDV
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
W
W
Fp
Fp
W
stupnIstuptuO
EO/RMn1NE_KNAB0NE_KNABxLES_VID4AQ-0AQ4BQ-0BQ4CQ-0CQ4DQ-0DQ
0X XX ZiHZiHZiHZiHorez
10 0 0 evitcAZiHZiHZiH2/NIf
11 00 evitcAevitcAZiHZiH2/NIf
10 10 evitcAevitcAevitcAZiH2/NIf
11 10 evitcAevitcAevitcAevitcA2/NIf
10 0 1 evitcAZiHZiHZiHNIf
11 0 1 evitcAevitcAZiHZiHNIf
10 1 1 evitcAevitcAevitcAZiHNIf
11 11 evitcAevitcAevitcAevitcANIf
xQ
ycneuqerf
8701I www.icst.com/products/hiperclocks.html REV. A MARCH 16, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8701I
LOW SKEW ¸1, ¸2
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage 4.6V
Inputs -0.5V to VDD + 0.5V
Outputs -0.5V to VDDO + 0.5V
Ambient Operating Temperature -40°C to 85°C
Storage Temperature -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of product at these condition or any conditions beyond
those listed in the
tions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
IDDVegatloVylppuSrewoPtupnI 531.33.3564.3V
ODDVegatloVylppuSrewoPtuptuO 531.33.3564.3V
DDItnerruCylppuSrewoPtnecseiuQ
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating condi-
V564.3=HIV=IDDV
V0=LIV
001Am
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDDI=VDDO=3.3V±5%, TA=-40°C TO 85°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,BLES_VID,ALES_VID
HIV
LIV
HII
LII
HOVegatloVhgiHtuptuO
LOVegatloVwoLtuptuO
tupnI
egatloVhgiH
tupnI
egatloVwoL
tupnI
tnerruChgiH
tupnI
tnerruCwoL
,0NE_KNAB
KLC_SOMCVLV564.3=IDDV28.3V
,0NE_KNAB
KLC_SOMCVLV564.3=IDDV3.0-3.1V
,0NE_KNAB
KLC_SOMCVLV564.3=NIV=IDDV051Aµ
,0NE_KNAB
KLC_SOMCVLV0=NIV,V564.3=IDDV5-Aµ
,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
EO/RMn,1NE_KNAB
V564.3=IDDV28.3V
V564.3=IDDV3.0-8.0V
V564.3=NIV=IDDV5Aµ
V0=NIV,V564.3=IDDV051-Aµ
V531.3=ODDV=IDDV
Am63-=HOI
V531.3=ODDV=IDDV
Am63=LOI
6.2V
5.0V
8701I www.icst.com/products/hiperclocks.html REV. A MARCH 16, 2001
4
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