ICST ICS8701CT, ICS8701CYT Datasheet
8701CY www.icst.com/products/hiperclocks.html REV. B AUGUST 2, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
GENERAL DESCRIPTION
The ICS8701 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS out-
puts are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can
be increased from 20 to 40 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1,
÷2 or a combination of ÷1 and ÷2 modes. The bank enable
inputs, BANK_EN0:1, support enabling and disabling each
bank of outputs individually. The master reset input, nMR/
OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS8701 is characterized at 3.3V and mixed 3.3V input
supply, and 2.5V output supply operating modes. Guaranteed
bank, output and part-to-part skew characteristics make the
ICS8701 ideal for those clock distribution applications demanding well defined performance and repeatability.
FEATURES
• 20 LVCMOS outputs, 7Ω typical output impedance
• 1 L VCMOS clock input
• Maximum output frequency up to 250MHz
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• Output skew: 250ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
BLOCK DIAGRAM PIN ASSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
nMR/OE
BANK_EN0
BANK_EN1
QAO - QA4
QB0 - QB4
QC0 - QC4
QD0 - QD4
CLK
48 47 46 45 44 43 42 41 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
QC3
VDDO
QC4
QD0
VDDO
QD1
GND
QD2
GND
QD3
V
DDO
QD4
QB1
V
DDO
QB0
QA4
VDDO
QA3
GND
QA2
GND
QA1
V
DDO
QA0
DIV_SELA
DIV_SELB
CLK
GND
VDDBANK_EN0
GND
BANK_EN1
VDDnMR/OE
DIV_SELC
DIV_SELD
GND
QB2
GND
QB3
V
DDO
QB4
QC0
V
DDO
QC1
GND
QC2
GND
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
ICS8701
HiPerClockS™
,&6
1
0
÷1
÷2
1
0
1
0
1
0
Bank Enable
Logic
8701CY www.icst.com/products/hiperclocks.html REV. B AUGUST 2, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERA T OR
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,5,2
,62,11
,53,23
44,14
V
ODD
rewoP.V5.2roV3.3ottcennoC.snipylppustuptuO
,81,9,7
,03,82,12
,64,93,73
84
DNGrewoP.dnuorgottcennoC.dnuorgylppusrewoP
02,61V
DD
rewoP.V3.3ottcennoC.snipylppusevitisoP
,72,52
,92
33,13
,1AQ,0AQ
,2AQ
4AQ,3AQ
tuptuO
.slevelecafretniSOMCVL.stuptuoAknaB
7
W
.ecnadepmituptuolacipyt
,63,43
,83
24,04
,1BQ,0BQ
,2BQ
4BQ,3BQ
tuptuO
.slevelecafretniSOMCVL.stuptuoBknaB
7
W
.ecnadepmituptuolacipyt
,54,34
,74
3,1
,1CQ,0CQ
,2CQ
4CQ,3CQ
tuptuO
.slevelecafretniSOMCVL.stuptuoCknaB
7
W
.ecnadepmituptuolacipyt
,6,4
,8
21,01
,1DQ,0DQ
,2DQ
4DQ,3DQ
tuptuO
slevelecafretniSOMCVL.stuptuoDknaB
7
W
.ecnadepmituptuolacipyt
22KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
31DLES_VIDtupnIpulluP
.stuptuoDknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
41CLES_VIDtupnIpulluP
.stuptuoCknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
32BLES_VIDtupnIpulluP
.stuptuoBknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
42ALES_VIDtupnIpulluP
.stuptuoAknabrofnoisividycneuqerfslortnoC
.slevelecafretniSOMCVL
91,71
,1NE_KNAB
0NE_KNAB
tupnIpulluP .slevelecafretniSOMCVL.sknabybstuptuoselbasiddnaselbanE
51EO/RMntupnIpulluP
.stuptuollaselbasiddnaselbanE.elbanetuptuodnateserretsaM
.slevelecafretniSOMCVL
8701CY www.icst.com/products/hiperclocks.html REV. B AUGUST 2, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FUNCTION TABLE
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C
NI
ecnaticapaCtupnI
KLC 4Fp
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,EO/RMN,0NE_KNAB
,1NE_KNAB
4
R
PULLUP
rotsiseRpulluPtupnI 15K
W
R
NWODLLUP
rotsiseRnwodlluPtupnI 15K
W
C
DP
ecnaticapaCnoitapissiDrewoP
)tuptuorep(
V
DD
V,
ODD
V564.3=Fp
V
DD
,V564.3=
V
ODD
V526.2=
Fp
R
TUO
ecnadepmItuptuO 7
W
stupnIstuptuO
EO/RMn1NE_KNAB0NE_KNABxLES_VID4AQ-0AQ4BQ-0BQ4CQ-0CQ4DQ-0DQ
xQ
ycneuqerf
0X XX ZiHZiHZiHZiHorez
10 0 0 evitcAZiHZiHZiH2/NIf
11 00 evitcAevitcAZiHZiH2/NIf
10 10 evitcAevitcAevitcAZiH2/NIf
11 10 evitcAevitcAevitcAevitcA2/NIf
10 0 1 evitcAZiHZiHZiHNIf
11 01 evitcAevitcAZiHZiHNIf
10 1 1 evitcAevitcAevitcAZiHNIf
11 11 evitcAevitcAevitcAevitcANIf
8701CY www.icst.com/products/hiperclocks.html REV. B AUGUST 2, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERA T OR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
DDx
4.6V
Inputs, V
I
-0.5V to VDD + 0.5V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance, θ
JA
47.9°C/W (0lfpm)
Storage T emperature, T
STG
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA =0°C TO 70°C
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
tupnI
egatloVhgiH
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
28.3V
KLC28.3V
V
LI
tupnI
egatloVwoL
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
V
DD
V564.3=3.0-8.0V
KLCV
DD
V564.3=3.0-3.1V
I
HI
tupnI
tnerruChgiH
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
V
DD
=V
NI
V564.3=5Aµ
KLCV
DD
=V
NI
V564.3=051Aµ
I
LI
tupnI
tnerruCwoL
,BLES_VID,ALES_VID
,DLES_VID,CLES_VID
,1NE_KNAB,0NE_KNAB
EO/RMn
V
DD
,V564.3=VNIV0=051-Aµ
KLCV
DD
,V564.3=VNIV0=5-Aµ
V
HO
egatloVhgiHtuptuO
V
DD
V=
ODD
V531.3=
I
HO
Am63-=
6.2V
V
LO
egatloVwoLtuptuO
V
DD
V=
ODD
V531.3=
I
LO
Am63=
5.0V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
egatloVylppuSevitisoP 531.33.3564.3V
V
ODD
egatloVylppuStuptuO 531.33.3564.3V
I
DD
tnerruCylppuSrewoPtnecseiuQ
V
DD
V=
HI
V564.3=
V
LI
V0=
59Am
TABLE 4B. LVCMOS DC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA =0°C TO 70°C
8701CY www.icst.com/products/hiperclocks.html REV. B AUGUST 2, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8701
LOW SKEW ÷1, ÷2
CLOCK GENERATOR
TABLE 5A. AC CHARACTERISTICS, V
DD
= V
DDO
= 3.3V±5%, TA =0°C TO 70°C
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