ICST ICS8532AY-01, ICS8532AY-01T Datasheet

Integrated Circuit Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
,&6
HiPerClockS
The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the out­puts during asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the ICS8532-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
The ICS8532-01 is a low skew, 1-to-17, Differ­ential-to-3.3V LVPECL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8532-01 has two selectable clock inputs.
FEATURES
17 differential 3.3V L VPECL outputs
Selectable CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential
input levels: L VDS, LVPECL, L VHSTL, SSTL, HCSL
PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
Maximum output frequency up to 500MHz
Translates any single-ended input signal (L VCMOS, L VTTL,
GTL) to 3.3V L VPECL levels with resistor bias on nCLK input
Output skew: 50ps (maximum)
Part-to-part skew: 250ps (maximum)
Propagation delay: 2.5ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
nQ1
nQ0
Q1
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0 - Q16 nQ0 - nQ16
VCCO
V
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
CLK_EN
V
CCO
Q0
52 51 50 49 48 47 46 45 44 43 42 41 40
1 2
nc
3
nc
4
CC
5 6 7 8 9 10
EE
11 12
nc
13
14 15 16 17 18 19 20 21 22 23 24 25 26
nQ16
ICS8532-01
Q15
nQ15
Q16
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
nQ2
Q3
Q2
nQ13
Q14
nQ14
T op View
nQ3
Q13
Q4
nQ12
nQ4
Q12
Q5
nQ11
nQ5
Q11
VCCO
VCCO
39
38 37 36 35 34 33 32 31 30 29 28 27
VCCO Q6 nQ6 Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 nc Vcco
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
1
Integrated Circuit Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
,62,31,1
V
04,93,72
4V
82,21,3,2cndesunU.tcennocoN 5KLCtupnInwodlluP.tupnikcolclaitnereffidgnitrevni-noN 6KLCntupnIpulluP.tupnikcolclaitnereffidgnitrevnI
7LES_KLCtupnInwodlluP
8KLCPtupnInwodlluP.tupnikcolcLCEPVLlaitnereffidgnitrevni-noN 9KLCPntupnIpulluP.tupnikcolcLCEPVLlaitnereffidgnitrevnI
01V
11NE_KLCtupnIpulluP
51,4161Q,61QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 71,6151Q,51QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 91,8141Q,41QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
12,0231Q,31QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 32,2221Q,21QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 52,4211Q,11QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 03,9201Q,01QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 23,139Q,9QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 43,338Q,8QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 63,537Q,7QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 83,736Q,6QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 24,145Q,5QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 44,344Q,4QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 64,543Q3QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 84,742Q,2QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 05,941Q,1QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD 25,150Q,0QntuptuO.levelecafretniLCEPVL.riaptuptuolaitnereffiD
:ETON
pulluP
OCC
CC
EE
dna
nwodlluP
rewoP.V3.3ottcennoC.snipylppustuptuO rewoP.V3.3ottcennoC.nipylppusevitisoP
rewoP.dnuorgottcennoC.nipylppusevitageN
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
.stupniKLCPn,KLCPstceles,HGIHnehW.tupnitceleskcolC
.stupniKLCn,KLCstceles,WOLnehW
.slevelecafretniLTTVL/SOMCVL
kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL
.seulavlacipytrofscitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
,KLC
KLCn
C
NI
R
PULLUP
R
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
NWODLLUP
ecnaticapaCtupnI
,KLCP
KLCPn
,NE_KLC LES_KLC
rotsiseRpulluPtupnI 15K
rotsiseRnwodlluPtupnI 15K
2
4Fp
4Fp
4Fp
Integrated Circuit Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS61Qurht0Q61Qnurht0Qn
00 KLCn,KLCWOL;delbasiDHGIH;delbasiD 01 KLCPn,KLCPWOL;delbasiDHGIH;delbasiD
10 KLCn,KLCdelbanEdelbanE 11 KLCPn,KLCPdelbanEdelbanE
.
1erugiFninwohssa
.
B3elbaTni
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuokcolceht,sehctiwsNE_KLCretfA
debircsedsastupniKLCPn,KLCPdnaKLCn,KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
nCLK, nPCLK
CLK, PCLK
CLK_EN
nQ0 - nQ16
Q0 - Q16
Disabled
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
KLCProKLCKLCPnroKLCn61Qurht0Q61Qnurht0Qn
01WOLHGIHlaitnereffiDotlaitnereffiDgnitrevnInoN
10 HGIHWOLlaitnereffiDotlaitnereffiDgnitrevnInoN 01ETON;desaiBWOLHGIH
11ETON;desaiBHGIHWOL
1ETON;desaiB0HGIHWOL
1ETON;desaiB1WOLHGIH
.sleveldedneelgnistpeccaottupni
FIGURE 1: CLK_EN TIMING DIAGRAM
Enabled
otdednEelgniS
laitnereffiD
otdednEelgniS
laitnereffiD
otdednEelgniS
laitnereffiD
otdednEelgniS
laitnereffiD
edoMtuptuOottupnIytiraloP
gnitrevnInoN
gnitrevnInoN
gnitrevnI
gnitrevnI
laitnereffidehtgniriwsessucsidhcihw,9erugiF,8egapnonoitcesnoitamrofnInoitacilppAehtotreferesaelP:1ETON
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
3
Integrated Circuit Systems, Inc.
ICS8532-01
LOW SKEW, 1-TO-17
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage Temperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
4.6V
-0.5V to VCC + 0.5V
-0.5V to V
CCO
+ 0.5V
40°C/W
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
CC
V
OCC
I
EE
egatloVylppuSevitisoP531.33.3564.3V egatloVylppuStuptuO531.33.3564.3V tnerruCylppuSrewoP 221051Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HI
V
LI
I
HI
I
LI
tnerruChgiHtupnI
tnerruCwoLtupnI
tnerruChgiHtupnI
tnerruCwoLtupnI
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
I
HI
I
LI
V
PP
V
RMC
2,1ETON
KLCV
tnerruChgiHtupnI
KLCV
tnerruCwoLtupnI
,NE_KLC LES_KLC ,NE_KLC LES_KLC
LES_KLCV
NE_KLCV
LES_KLCV
NE_KLCV
= V
CC
NI
KLCnV
KLCnV
NI
NI
NI
egatloVtupnIkaeP-ot-kaeP 51.03.1V
;egatloVtupnIedoMnommoC
VsadenifedsiegatlovedomnommoC:1ETON
.
HI
= 3.3V±5%, TA = 0°C TO 70°C
CCO
= V
CC
NI
NI
NI
NI
CCO
V= V=
= 3.3V±5%, TA = 0°C TO 70°C
CCO
V=
CC
V=
CC
V,V0= V,V0=
V564.3=051Aµ
V564.3=5Aµ
CC
CC
V564.3=5-Aµ V564.3=051-Aµ
= 3.3V±5%, TA = 0°C TO 70°C
CC
CC
V,V0= V,V0=
V564.3=051Aµ V564.3=5Aµ
CC
CC
V564.3=5-Aµ V564.3=051-Aµ
2567.3V
3.0-8.0V
V
5.0+V
EE
VsiKLCndnaKLCrofegatlovtupnimumixameht,snoitacilppadedneelgnisroF:2ETON
.V3.0+
58.0-V
CC
8532AY-01 www.icst.com/products/hiperclocks.htlm REV. B AUGUST 9, 2001
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