inputs. The CLK, nCLK pair can accept most standard
differential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels. The clock enable is
internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output skew and part-to-part skew characteristics make the ICS8531-01 ideal for high performance workstation and server applications.
The ICS8531-01 is a low skew , high performance
1-to-9 Differential-to-3.3V L VPECL Fanout Buffer
and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS. The ICS8531-01 has two selectable clock
FEATURES
• 9 differential 3.3V L VPECL outputs
• Selectable CLK, nCLK or L VPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: L VDS, L VPECL, L VHSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 500MHz
• Translates any single ended input signal (L VCMOS, L VTTL,
GTL) to 3.3V L VPECL levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAMPIN ASSIGNMENT
V
CCO
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
VCC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
EE
V
CLK_EN
7mm x 7mm x 1.4mm package body
Q0
32 31 30 29 28 27 26 25
1
2
3
4
ICS8531-01
5
6
7
8
9 10 11 12 13 14 15 16
nQ8
Vcco
32-Lead LQFP
nQ1
nQ0
Q1
Q7
nQ7
Q8
Y package
Top View
Q2
nQ6
nQ2
Q6
VCCO
Vcco
24
23
22
21
20
19
18
17
CCO
V
Q3
nQ3
Q4
nQ4
Q5
nQ5
CCO
V
8531AY-01www.icst.com/products/hiperclocks.htmlREV. B AUGUST 9, 2001
8531AY-01www.icst.com/products/hiperclocks.htmlREV. B AUGUST 9, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8531-01
LOW SKEW, 1-TO-9
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage T emperature, T
CCx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
ods may affect product reliability .
4.6V
-0.5V to VCC + 0.5V
-0.5V to V
CCO
+ 0.5V
47.9°C/W
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for extended peri-