ICST ICS8525BG, ICS8525BG-T Datasheet
Integrated
Circuit
Systems, Inc.
ICS8525
LOW SKEW, 1-TO-4
LVCMOS-TO-L VHSTL FANOUT BUFFER
GENERAL DESCRIPTION
,&6
HiPerClockS™
cept LVCMOS or LVTTL input levels and translate them to
1.8V L VHSTL levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8525 ideal for those applications demanding
well defined performance and repeatability.
The ICS8525 is a low skew, high performance
1-to-4 L VCMOS-to-LVHSTL fanout buf fer and a
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8525 has two selectable clock inputs that ac-
FEATURES
• 4 differential 1.8V L VHSTL outputs
• Selectable LVCMOS / LVTTL clock inputs for redundant
and multiple frequency fanout applications
• Maximum output frequency up to 266MHz
• Translates L VCMOS and LVTTL levels to 1.8V
L VHSTL levels
• Output skew: 35ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V core, 1.8V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM PIN ASSIGNMENT
CLK_EN
CLK0
CLK1
CLK_SEL
D
Q
LE
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
6.5mm x 4.4mm x 0.92mm Package Body
GND
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
DD
20-Lead TSSOP
20
1
19
2
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
10
ICS8525
G Package
T op View
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001
1
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
rebmuNemaNepyTnoitpircseD
1DNGrewoP.dnuorgottcennoC.dnuorgylppusrewoP
2NE_KLCtupnIpulluP
3LES_KLCtupnInwodlluP
40KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
61KLCtupnInwodlluP.tupnikcolcLTTVL/SOMCVL
9,8,7,5cndesunU.tcennocoN
01V
81,31V
21,113Q,3QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
51,412Q,2QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
71,611Q,1QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
02,910Q,0QntuptuO.slevelecafretniLTSHVL.riaptuptuolaitnereffiD
pulluP
:ETON
DD
ODD
dna
nwodlluP
rewoP.V3.3ottcennoC.nipylppusevitisoP
rewoP.V8.1ottcecnnoC.snipylppustuptuO
ICS8525
LOW SKEW, 1-TO-4
LVCMOS-TO-L VHSTL FANOUT BUFFER
kcolcwollofstuptuokcolc,HGIHnehW.elbanekcolcgnizinorhcnyS
.hgihdecroferastuptuoQn,woldecroferastuptuoQ,WOLnehW.tupni
.slevelecafretniLTTVL/SOMCVL
.tupni1KLCstceles,HGIHnehW.tupnitceleskcolC
.slevelecafretniLTTVL/SOMCVL.tupni0KLCstceles,WOLnehW
.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer
TABLE 2. PIN CHARACTERISTICS
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
C
NI
R
PULLUP
R
NWODLLUP
1KLC,0KLC4Fp
ecnaticapaCtupnI
rotsiseRpulluPtupnI 15KΩ
,NE_KLC
LES_KLC
rotsiseRnwodlluPtupnI 15KΩ
4Fp
8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001
2
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
stupnIstuptuO
NE_KLCLES_KLCecruoSdetceleS3Qurht0Q3Qnurht0Qn
00 0KLCWOL;delbasiDHGIH;delbasiD
01 1KLCWOL;delbasiDHGIH;delbasiD
10 0KLCdelbanEdelbanE
11 1KLCdelbanEdelbanE
.1erugiFninwohssa
ICS8525
LOW SKEW, 1-TO-4
LVCMOS-TO-L VHSTL FANOUT BUFFER
egdekcolctupnignillafdnagnisiragniwollofdelbanerodelbasiderastuptuookcolceht,sehctiwsNE_KLCretfA
.B3elbaTnidebircsedsastupni1KLCdna0KLCehtfonoitcnufaerastuptuoehtfoetatseht,edomevitcaehtnI
CLK0, CLK1
CLK_EN
nQ0 - nQ3
Q0 - Q3
TABLE 3B. CLOCK INPUT FUNCTION TABLE
stupnIstuptuO
1KLCro0KLC3Qurht0Q3Qnurht0Qn
0WOLHGIH
1HGIHWOL
EnabledDisabled
FIGURE 1 - CLK_EN TIMING DIAGRAM
8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001
3
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-4
ICS8525
LVCMOS-TO-L VHSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
Inputs, V
I
Outputs, V
Package Thermal Impedance, θ
Storage Temperature, T
DDx
O
JA
STG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics
or
AC Characteristics
extended periods may affect product reliability.
4.6V
-0.5V to VDD + 0.5V
-0.5V to V
DDO
+ 0.5V
73.2°C/W (0lfpm)
-65°C to 150°C
is not implied. Exposure to absolute maximum rating conditions for
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
= 3.3V±5%, V
DD
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
DD
V
ODD
I
DD
egatloVylppuSevitisoP531.33.3564.3V
egatloVylppuStuptuO6.18.10.2V
tnerruCylppuSrewoP 05Am
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
1KLC,0KLC2567.3V
V
HI
V
LI
I
HI
I
LI
egatloVhgiHtupnI
,NE_KLC
LES_KLC
1KLC,0KLC3.0-3.1V
egatloVwoLtupnI
,NE_KLC
LES_KLC
,1KLC,0KLC
tnerruChgiHtupnI
LES_KLC
NE_KLCV
,1KLC,0KLC
tnerruCwoLtupnI
LES_KLC
V
NE_KLCV
= 3.3V±5%, V
DD
V=
V
DD
NI
V=
DD
NI
DD
DD
= 1.8V±0.2V , TA = 0°C TO 70°C
DDO
= 1.8V±0.2V, TA = 0°C TO 70°C
DDO
2567.3V
3.0-8.0V
V564.3=051Aµ
V564.3=5Aµ
V,V564.3=
V0=5-Aµ
NI
V,V564.3=
V0=051-Aµ
NI
TABLE 4C. L VHSTL DC CHARACTERISTICS, V
= 3.3V±5%, V
DD
= 1.8V±0.2V , TA = 0°C TO 70°C
DDO
lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU
V
HO
V
LO
V
XO
V
GNIWS
1ETON
1ETON
kaeP-ot-kaeP
;egatloVhgiHtuptuO
;egatloVwoLtuptuO
egatloVrevossorCtuptuOV(x%04
gniwSegatloVtuptuO
12.1V
04.0V
HOV-LO
V+)
LO
V(x%06
HOV-LO
V+)
V
LO
57.052.1V
05htiwdetanimretstuptuO:1ETON Ω .DNGot
8525BG www.icst.com/products/hiperclocks.html REV. B JULY 27, 2001
4
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