ICST ICS672M-01, ICS672M-01T, ICS672M-02, ICS672M-02I, ICS672M-02IT Datasheet

ICS672-01/02

QuadraClock™ Quadrature Delay Buffer

Description

The ICS672-01 and ICS672-02 are zero delay
buffers that generate four output clocks whose
phases are spaced at 90° intervals. Based on ICS’
proprietary low jitter Phase Locked Loop (PLL)
techniques, each device provides five low skew
outputs, with clock rates up to 84 MHz for the
ICS672-01 and up to 135 MHz for the
ICS672-02. By providing outputs delayed one
quarter clock cycle, the device is useful for systems
requiring early or late clocks.

The ICS672-01/02 include multiplier selections of
x0.5, x1, x2, x3, x4, x5, or x6. They also offer a
mode to power down all internal circuitry and tri
state the outputs. In normal operation, output
clock FBCLK is tied to the FBIN pin.

ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.

Features

• Packaged in 16 pin narrow SOIC

• Input clock range from 10 MHz to 150 MHz

• Clock outputs from up to 84 MHz (ICS672-01)
and up to 135 MHz (ICS672-02)

• Zero input-output delay

• Integrated x0.5, x1, x2, x3, x4, x5, or x6 selections

• Four accurate (<250 ps) outputs with 0°, 90°,
180°, and 270° phase shift from ICLK, and one
FBCLK (0°)

• Separate supply for output clocks from 2.5V to 5V

• Full CMOS outputs (TTL compatible)

• Tri state mode for board-level testing

• Includes Power Down for power savings

• Advanced, low power, sub-micron CMOS process

• 3.3 V to 5 V operating voltage

Block Diagram

IN

FBIN

S2:S0

• Industrial temperature version available

GND

2 3

PLL

Multiplier

and

Quadrature

Generation

3

Control

Logic

Power Down + Tri-State

VDDIOVDD

CLK0
CLK90

CLK180
CLK270

CLKFB

External Feedback

MDS 672-01/02 C 1 Revision 112200

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• [phone] tel • www.icst.com

ICS672-01/02

QuadraClock™ Quadrature Delay Buffer

Pin Assignment

ICS672-01/02

CLK90

CLK270

VDDIO

GND
GND

S0

16

1
2
3
4

5
6
7
8

15
14

13
12

11
10

9

FBINICLK
FBCLK
CLK0CLK180
VDD
GND
VDD

S2
S1

Output Clock Mode Select Table

S2 S1 S0 Output Clocks

0 0 0 Power Down + Tri State
0 0 1 x1
0 1 0 x2
0 1 1 x3
1 0 0 x4
1 0 1 x5
1 1 0 x6
1 1 1 x0.5

16 pin narrow (150 mil) SOIC

Pin Descriptions

Number Name Type Description

1 ICLK I Clock Input.
2 CLK90 O Clock Output (90° delayed from CLK0).
3 CLK180 O Clock Output (180° delayed from CLK0).
4 CLK270 O Clock Output (270° delayed from CLK0).
5 VDDIO P Supply voltage for input and output clocks. Must not exceed VDD.

6, 7, 12 GND P Connect to ground.

8 S0 I Select input 0. See table above.
9 S1 I Select input 1. See table above.

10 S2 I Select input 2. See table above.

11, 13 VDD P Connect to +3.3 V or +5.0 V.

14 CLK0 O Clock Output phase aligned to ICLK.
15 FBCLK O Feedback Clock Output (0° phase shift from CLK0).
16 FBIN I Feedback Clock Input. In normal operation, connect to FBCLK

Key: I = Input; O = output; P = power supply connection.

External Components

The ICS672-01/01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND on pins 11 and 12, VDD and GND
on pins 13 and 12, and VDDIO and GND on pins 5 and 6, as close to the device as possible. A series
termination resistor of 33 Ω may be used close to each clock output pin to reduce reflections.

MDS 672-01/02 C 2 Revision 112200

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• [phone] tel • www.icst.com