The ICS650-21 is a low cost, low jitter, high
performance clock synthesizer for system
peripheral applications. Using analog/digital
Phase-Locked Loop (PLL) techniques, the device
accepts a parallel resonant 25 MHz crystal input to
produce up to eight output clocks. The device
provides clocks for PCI, SCSI, Fast Ethernet,
Ethernet, USB, and AC97. The user can select one
of three USB frequencies, and also one of two
AC97 audio frequencies. The OE pin puts all
outputs into a high impedance state for board level
testing. All frequencies are generated with less than
one ppm error, meeting the demands of SCSI and
Ethernet clocking.
The ICS650 can be mask customized to produce
any frequencies from 1 to 150 MHz.
Block Diagram
Features
• Packaged in 20 pin tiny SSOP (QSOP)
• Lower jitter version of ICS650-01
• Operating VDD of 3.3V or 5V
• Zero ppm synthesis error in all clocks
• Inexpensive 25 MHz crystal or clock input
• Provides Ethernet and Fast Ethernet clocks
• Provides SCSI clocks
• Provides PCI clocks
• Selectable AC97 audio clock
• Selectable USB clock
• OE pin tri-states the outputs for testing
• Selectable frequencies on three clocks
• Duty cycle of 45/55 for Processor clock and Audio
clock
• Advanced, low power CMOS process
PSEL1:0
ASEL
USEL
25 MHz
crystal
or clock
MDS 650-21 A1 Revision 010301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
0 = connect directly to ground, 1 = connect directly
20 pin (150 mil) SSOP
to VDD, M=leave unconnected (floating)
Pin Descriptions
Pin #Name TypeDescription
1USELIUCLK Select pin. Determines frequency of USB clock per table above.
2X2XOCrystal connection. Connect to parallel mode 25 MHz crystal. Leave open for clock.
3X1/ICLKXICrystal connection. Connect to parallel mode 25 MHz crystal, or clock.
4VDDPConnect to VDD. Must be same value as other VDD. Decouple with pin 6.
5VDDPConnect to VDD. Must be same value as other VDD.
6GNDPConnect to ground.
7
820MOFixed 20 MHz output for Ethernet.
9ACLKOAC97 Audio clock output per table above.
1025MOFixed 25 MHz reference output for Fast Ethernet.
11OEIOutput Enable. Tri-states all outputs when low.
12PCLK1OPCLK output number 1 per table above.
13OFF/14.318MO14.31818 MHz clock output only when ASEL=VDD.
14GNDPConnect to ground.
15ASELIACLK Select pin. Determines frequency of Audio clock per table above.
16VDDPConnect to VDD. Must be same value as other VDD. Decouple with pin 14.
17PCLK3OPCLK output number 3 per table above.
18PCLK2OPCLK output number 2 per table above.
19PSEL0IProcessor Select pin #0. Determines frequencies on PCLKs 1-3 per table above.
20PSEL1IProcessor Select pin #1. Determines frequencies on PCLKs 1-3 per table above.
UCLKOUSB clock output per table above.
Key: I = Input; XO/XI = crystal connections; O = output; P = power supply connection
MDS 650-21 A2 Revision 010301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ABSOLUTE MAXIMUM RATINGS (note 1)
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With all clocks at highest frequencies.
ICS650-21
System Peripheral Clock Source
Electrical Specifications
ParameterConditionsMinimumTypicalMaximumUnits
Supply voltage, VDDReferenced to GND7V
Inputs and Clock OutputsReferenced to GND-0.5VDD+0.5V
Ambient Operating Temperature070C
Soldering TemperatureMax of 10 seconds260C
Storage temperature-65150C
Operating Voltage, VDD 3.05.5V
Input High Voltage, VIHSelect inputs, OE2V
Input Low Voltage, VILSelect inputs, OE0.8V
Output High Voltage, VOHVDD=3.3V, IOH=-8mA2.4V
Output Low Voltage, VOLVDD=3.3V, IOL=8mA0.4V
Output High Voltage, VOH, VDD = 3.3 or 5VIOH=-8mAVDD-0.4V
Operating Supply Current, IDD, at 5V No Load, note 250mA
Operating Supply Current, IDD, at 3.3VNo Load, note 230mA
Short Circuit Current, VDD = 3.3 Each output±50mA
Input CapacitanceExcept X15pF
Input Crystal or Clock Frequency25.000MHz
Output Clocks Accuracy (synthesis error)All clocks1ppm
Output Clock Rise Time0.8 to 2.0V1.5ns
Output Clock Fall Time2.0 to 0.8V1.5ns
Output Clock Duty Cycle, UCLCKAt VDD/2405060%
Output Clock Duty Cycle, PCLCK, ACLCKAt VDD/2455055%
One Sigma Jitter, except ACLK75ps
One Sigma Jitter, ACLK120ps
Absolute Clock Period Jitter PCLK, UCLK, 20M
Notes:1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
- 500500ps
External Components
The ICS650 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1µF should be connected between VDD and GND (on pins 4 and 6, and pins 16 and 14),
as close to the chip as possible. A series termination resistor of 33Ω may be used for each clock output. The
25.000 MHz crystal must be connected as close to the chip as possible. The crystal should be a fundamental
mode, parallel resonant, 30ppm or better (to meet the Ethernet specs). Crystal capacitors should be
connected from pins X1 to ground and X2 to ground. The value of these capacitors is given by the
following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-12) x 2. So for a
crystal with 16pF load capacitance, two 8pF caps should be used. If a clock input is used, drive it into X1
and leave X2 unconnected.
MDS 650-21 A3 Revision 010301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
PRELIMINARY INFORMATION
AREA
Inches
Millimeters
System Peripheral Clock Source
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
ICS650R-21TICS650R-2120 pin SSOPTape and Reel0 to 70° C
ICS650R-21IICS650R-21I20 pin SSOPTubes-40 to 85° C
ICS650R-21ITICS650R-21I20 pin SSOPTape and Reel-40 to 85° C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 650-21 A4 Revision 010301
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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