ICST ICS650R-14, ICS650R-14I, ICS650R-14IT, ICS650R-14T Datasheet

ICS650-14B

Networking System Clock

MDS 650-14B A 1 Revision 082800 Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•[phone]tel• www.icst.com

PRELIMINARY INFORMATION

The ICS650-14B is a low cost, low jitter, high
performance clock synthesizer customized for
networking systems applications. Using analog
Phase-Locked Loop (PLL) techniques, the device
accepts a 25.0 MHz clock or fundamental mode
crystal input to produce multiple output clocks of
one fixed 25.0 MHz, a four (plus one) frequency
selectable bank, and two frequency selectable
clocks. All output clocks are frequency locked
together. The ICS650R-14B outputs
all have 0 ppm synthesis error.

Block Diagram

Description Features

• Packaged in 20 pin (150 mil) SSOP (QSOP)

• 25.00 MHz fundamental crystal or clock input

• One fixed output clock of one 25.0 MHz

• One bank of four frequency selectable
output clocks

• Three frequency selectable clock outputs

• Zero ppm synthesis error in all clocks

• Ideal for networking systems

• Full CMOS output swing

• Advanced, low power, sub-micron CMOS process

• 3.0V to 5.5V operating voltage

• Industrial temperature range available

Clock

Buffer/

Crystal

Oscillator

VDD GND

Clock Synthesis

and Control

Circuitry

25.00 MHz
crystal or clock

25.00 MHz

2

2

Output

Buffer

CLKA5

Output

Buffer

X1/ICLK

X2

CLKB

Output

Buffer

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

OE (All outputs)

Output

Buffer

CLKA 1:4

4

SELA 0:1

2

SELB 0:1

2

SELC

CLKC

Output

Buffer

ICS650-14B

Networking System Clock

MDS 650-14B A 2 Revision 082800 Printed 11/15/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•[phone]tel• www.icst.com

PRELIMINARY INFORMATION

Pin Descriptions

Key: XI, XO = crystal connections; I = Input; I(Pu) = Input with pull up O = Output; P = power supply connection; TI = tri level input

Number Name Type Description

1 SELB0 T I Select pin for CLKB. See Table 2.
2 X2 XO Crystal connection. Connect to 25 MHz crystal or leave unconnected for a clock input.
3 X1/ICLK XI Crystal connection. Connect to 25 MHz fundamental crystal or clock input.
4 VDD P Connect to +3.3 V or +5 V. Must be same as other VDDs.
5 SELB1 I(Pu) Select pin for CLK B. See table 2.
6 GND P Connect to ground.
7 CLKB O Selectable clock output. See Table 2.
8 CLKC O Selectable clock output. See Table 3.

9 CLKA5 O Selectable clock output. See Table 1.
10 25M O 25.0 MHz clock output.
11 OE I(Pu) Output Enable. Tri-states all output clocks when low. Internal pull-up.
12 CLKA1 O Selectable clock output. See Table 1.
13 CLKA4 O Selectable clock output. See Table 1.
14 GND P Connect to ground.
15 SELA1 T I Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
16 VDD P Connect to +3.3V or +5.0V. Must be same as other VDDs.
17 CLKA3 O Selectable clock output. See Table 1.
18 CLKA2 O Selectable clock output. See Table 1.
19 SELA0 T I Select pin for CLKA1:4 and CLKA5 outputs. See Table 1.
20 SELC TI Select pin for CLKC output. See Table 3.

Pin Assignment

1

16

2
3

4

15
14
13

VDD

CLKA5

X2

VDD

20 pin (150 mil) SSOP

5
6

7
8

12

11

10

9

25M

SELA0

X1/ICLK

SELB0

CLKA2

SELC

CLKA3

CLKA1
OE

CLKC

CLKB

18
17

19

20

GND

SELB1

CLKA4

GND

SELA1

SELC CLKC

0 CLKB/4

M 62.5

1 125

Table 3

0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)

SELB1 SELB0 CLKB

0 0 30
0 M 27
0 1 48
1 0 83.33
1 M 19.44
1 1 80

Table 2

SELA1 SELA0 CLKA1:4 CLKA5

0 0 33.33 66.66
0 M 50 75

0 1 66.67 133.33
M 0 100 33.33
M M 33.33 83.33
M 1 50 125

1 0 33.33 100

1 M 25 75

1 1 66.67 100

Table 1