ICST ICS650R-12, ICS650R-12T Datasheet

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• [phone]tel • www.icst.com

Description Features

ICS650-12

MPEG Clock Synthesizer

The ICS650-12 is a low cost, low jitter, high
performance clock synthesizer designed to
produce fixed clock outputs of 13.5 MHz and

27.0 MHz and four selectable clock outputs of two
Processor Clocks (PCLK1 and PCLK2), Audio
Clock (ACLK), and Communications Clock
(CCLK). Using our patented analog Phase­Locked Loop (PLL) techniques, the device uses a

27.0 MHz clock or fundamental crystal input to
produce clocks ideal for Digital Video/MPEG­based applications.

Block Diagram

PS2:0

Synthesis

AS2:0

Control

Circuitry

CS1:0

• Packaged in 20 pin tiny SSOP (QSOP)

• Input Frequency of 27.0 MHz

• Zero ppm synthesis error in output clocks

• Provides fixed 13.5 MHz and 27.0 MHz.
Also provides two selectable Processor Clocks,
one Audio Clock, and one Communications Clock

• Ideal for Digital Video/MPEG-based applications

• 3.3 V or 5.0 V operating voltage

• Entire chip powers down (when CS1=CS0=0)

Clock

and

Output

Buffer

Output

Buffer

Output

Buffer

Output

Buffer

PCLK1

PCLK2

ACLK

CCLK

Output

Buffer

÷ 2

Input

27.0 MHz
crystal or
clock

MDS 650-12 A 1 Revision 113000

Buffer/Crystal

Oscillator

Output

Buffer

13.5 MHz

27.0 MHz

ICS650-12

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• [phone]tel • www.icst.com

MPEG Clock Synthesizer

Pin Assignment

PS2

X2
X1

VDD

CS1

GND

ACLK

PCLK1

CS0
AS2

1

2

3
4

5
6

7
8

9

20 pin SSOP (QSOP)

20
19

18
17

16
15

14
13

12
1110

PS1
PS0

CCLK
PCLK2

VDD

AS1
GND

13.5M
27M

AS0

PCLK1 and PCLK2 Select Table (in MHz)

PS2 PS1 PS0 PCLK1 PCLK2

0 0 0 108.00 54.00
0 0 1 55.00 27.5
0 1 0 66.67 33.33
0 1 1 80.00 40.00
1 0 0 54.00 27.00
1 0 1 81.00 40.5
1 1 0 50.00 25.00
1 1 1 60.00 30.00

ACLK Select Table (in MHz)

AS2 AS1 AS0 ACLK

0 0 0 12.288
0 0 1 11.2896
0 1 0 8.192
0 1 1 24.576

CCLK Select Table (in MHz)

CS1 CS0 CCLK

0 0 All off*
0 1 20.00
1 0 66.6666
1 1 24.576

1 0 0 8.192
1 0 1 16.9344
1 1 0 18.432
1 1 1 11.2896

*Note: Entire chip powers
down (outputs stop low)
when CS1 = CS0 = 0.

Pin Descriptions

Pin # Name Type Description

1 PS2 I Processor Clock Select Pin 2. See above table.
2 X2 XO Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input
3 X1 XI Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.

4, 16 VDD P Connect to +3.3 V or +5.0 V.

5 CS1 I Communications Clock Select Pin 1. See above table.

6, 14 GND P Connect to ground.

7 ACLK O Audio Clock Output. See above table.
8 PCLK1 O Processor Clock Output 1. See above table.

9 CS0 I Communications Clock Select 0. See above table.
10 AS2 I Audio Clock Select Pin 2. See above table.
11 AS0 I Audio Clock Select Pin 0. See above table.
12 27M O 27 MHz buffered clock output.
13 13.5M O 13.5 MHz clock output.
15 AS1 I Audio Clock Select Pin 1. See above table.
17 PCLK2 O Processor Clock Output 2. See above table.
18 CCLK O Communications Clock Output. See above table.
19 PS0 I Processor Clock Select Pin 0. See above table.
20 PS1 I Prcoessor Clock Select Pin 1. See above table.

Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal
connections

MDS 650-12 A 2 Revision 113000