ICST ICS620-01RT, ICS620-01R Datasheet
PRELIMINARY INFORMATION
ICS620-01
ICRO
C
LOCK
Description
The ICS620-01 is a low cost, low jitter, high
performance clock synthesizer for digital still
cameras. Using analog Phase-Locked Loop
(PLL) techniques, the device uses a
14.318 MHz crystal input to produce multiple
output clocks required in the camera. It
provides selectable NTSC/PAL clock, a
selectable processor clock, a selectable CCD
clock, and a selectable interface clocks. Most
clocks are generated to a very low ppm
synthesis error rate.
All clocks can be turned off using a power
down mode. Custom versions with userdefined frequencies and power down modes
are available in 6-8 weeks.
Digital Still Camera Clock Source
Features
• Packaged in 28 pin, 150 mil wide SSOP (QSOP)
• Provides all clocks necessary for many digital still
camera systems
• All clocks are frequency locked together
• Interface clock for USB, P1394, or UART
• Saves space over multiple crystals and oscillators
• Clocks power down when all select pins are low
• Full CMOS outputs also compatible with TTL levels
• +3.3 V or +5 V operation
• Low power, sub-micron CMOS process
• Custom versions available
Block Diagram
NSEL1:0
PSEL1:0
CSEL1:0
ISEL1:0
X1
X2
14.31818
MHz
crystal
2
2
2
2
Crystal
Oscillator
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
PLL Clock
Synthesis
Circuitry
÷2
÷2
÷2
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
Output
Buffer
NTSC/PAL Clock 1
NTSC/PAL Clock 2
Processor Clock 1
Processor Clock 2
CCD Clock 1
CCD Clock 2
Interface Clock 1
Interface Clock 2
MDS 620-01 B 1 Revision 072098 Printed 12/4/00
Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
PRELIMINARY INFORMATION
Power down both
Power Down - both outputs stop low
Power down
Power down both
ICS620-01
Digital Still Camera Clock Source
Clock C Frequency Select Table (MHz)
CSEL1 CSEL0 CLKC1 CLKC2 Actual error
0 0
0 M 14.31818 7.15909 0 ppm
0 1 9.81818 4.90909 0 ppm
M 0 7.3728 3.6864 31 ppm high
M M 27 13.5 0 ppm
M 1 8 4 0.017% high
1 0 28 14 0 ppm
1 M 24.54545 12.272725 11 ppm high
1 1 32 16 0.017% high
Key: 0 = connect to ground, 1 = connect to VDD,
Pin
Assignment
ICRO
CSEL0
NC
X2
X1
VDD
NSEL1
VDD
VDD
NSEL0
GND
GND
CLKI2
CLKI1
CLKP2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C
LOCK
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CSEL1
ISEL0
NC
CLKN1
ISEL1
GND
CLKN2
VDD
PSEL0
GND
CLKC1
CLKC2
PSEL1
CLKP1
M = leave unconnected (floating).
Processor Clock Select (MHz)
PSEL1 PSEL0 CLKP1 CLKP2
0 0
0 1 20.50 10.25
1 0 23.96 11.98
1 1 24.5455 12.2727
Interface Clock Select (MHz)
ISEL1 ISEL0 CLKI1 CLKI2
0 0
0 1 36.864 18.432
1 0 24.576 8.192
1 1 48 12
NTSC/PAL Clock Select (MHz)
NSEL1 NSEL0 CLKN1 CLKN2 Error
0 0
0 M 8.8672 4.43361 2 ppm low
0 1 27 13.5 0 ppm
1 0 35.4688 17.7344 2 ppm low
1 M 7.1591 3.5795 0 ppm
1 1 28.6364 14.3182 0 ppm
Pin Descriptions
Pin # Name Type Description
1 CSEL0 TI C clock SELect pin 0.
2, 26 NC - No Connect. Nothing is connected internally to this pin.
3 X2 XO Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
4 X1 XI Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
5, 7, 8, 21 VDD P Connect to +3.3V or +5V. Must be same voltage on all pins.
6 NSEL1 I NTSC/PAL SELect pin 1.
9 NSEL0 TI NTSC/PAL SELect pin 0.
10, 11, 19, 23 GND P Connect to Ground.
12 CLKI2 O Interface CLocK output 2.
13 CLKI1 O Interface CLocK output 1.
14 CLKP2 O Processor CLocK output 2.
15 CLKP1 O Processor CLocK output 1.
16 PSEL1 I Processor clock SELect pin 1.
17 CLKC2 O C CLocK output 2.
18 CLKC1 O C CLocK output 1.
20 PSEL0 I Processor clock SELect pin 0.
22 CLKN2 O NTSC/PAL CLocK output 2.
24 ISEL1 I Interface clock SELect pin 1.
25 CLKN1 O NTSC/PAL CLocK output 1. Output may stop high or low during power down.
27 ISEL0 I Interface clock SELect pin 0.
28 CSEL1 TI C clock SELect pin 1.
Key: I = Input, O = Output, P = Power supply connection, TI = tri-level input (automatically biased to M level if unconnected).
Internal pull-ups are on pins 6, 16, 20, 24, and 27.
MDS 620-01 B 2 Revision 072098 Printed 12/4/00
Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
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