ICST ICS571M, ICS571MT Datasheet
PRELIMINARY INFORMATION
Low Phase Noise Zero Delay Buffer
ICS571
Description
The ICS571 is a high speed, high output drive, low
phase noise Zero Delay Buffer (ZDB) which
integrates ICS’ proprietary analog/digital Phase
Locked Loop (PLL) techniques. ICS introduced
the world standard for these devices in 1992 with
the debut of the AV9170, and updated that with
the ICS570. The ICS571, part of ICS’
ClockBlocks™ family, was designed to operate at
higher frequencies, with faster rise and fall times,
and with lower phase noise. The zero delay feature
means that the rising edge of the input clock aligns
with the rising edges of both outputs, giving the
appearance of no delay through the device. There
are two outputs on the chip, one being a low-skew
divide by two of the other.
The chip is ideal for synchronizing outputs in a
large variety of systems, from personal computers
to data communications to video. By allowing offchip feedback paths, the ICS571 can eliminate the
delay through other devices. The use of dividers in
the feedback path will enable the part to multiply
by more than two.
Features
• Packaged in 8 pin SOIC.
• Can function as low phase noise x2 multiplier.
• Low skew outputs. One is ÷2 of other.
• Input clock frequency up to 160 MHz at 3.3V.
• Phase noise of better than -100 dBc/Hz from
1kHz to 1MHz offset from carrier
• Can recover poor input clock duty cycle.
• Output clock duty cycle of 45/55 at 3.3V.
• High drive strength for >100 MHz outputs.
• Full CMOS clock swings with 25mA drive
capability at TTL levels.
• Advanced, low power CMOS process.
• Operating voltages of 3.0 to 5.5 V.
Block Diagram
ICLK
FBIN
External feedback can come from CLK or CLK/2 (see table on page 2).
MDS 571 B 1 Revision 072899 Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
÷2
Output
Buffer
Output
Buffer
CLK
CLK/2
Pin Assignment
PRELIMINARY INFORMATION
ICS571
Low Phase Noise Zero Delay Buffer
ICLK
VDD
GND
CLK/2
1 8
2
3
4
FBIN
7
CLK
6
VDD
5
GND
Feedback Configuration Table and Frequency Ranges (at 3.3V)
Feedback From CLK CLK/2 Input Range
CLK Input clock frequency Input clock frequency/2 20 -160 MHz
CLK/2 2xInput clock frequency Input clock frequency 10 - 80 MHz
Pin Descriptions
Number Name Type Description
1 ICLK CI Reference clock input.
2 VDD P Connect to +3.3V or +5V. Must be same as other VDD.
3 GND P Connect to ground.
4 CLK/2 O Clock output per Table above. Low skew divide by two of pin 7 clock.
5 GND P Connect to ground.
6 VDD P Connect to +3.3V or +5V. Must be same as other VDD.
7 CLK O Clock output per Table above.
8 FBIN CI Feedback clock input. Connect to CLK or CLK/2 per table above.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS571 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND on each
side of the chip (between pins 2 and 3, and also between pins 6 and 5). They must be connected close to
the ICS571 to minimize lead inductance. No external power supply filtering is required for this device.
A 33 Ω terminating resistor can be used next to each output pin.
MDS 571 B 2 Revision 072899 Printed 11/14/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
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