PRELIMINARY INFORMATION
outputs).
• Low skew (100 ps) outputs.
• Ability to choose between 14 different
multipliers from 0.5X to 32X.
• Input clock frequency up to 150 MHz at 3.3V.
• Can recover degraded input clock duty cycle.
• Output clock duty cycle of 45/55.
• Power Down and Tri-State Mode.
• Full CMOS clock swings with 25mA drive
capability at TTL levels.
• Advanced, low power CMOS process.
• Operating voltage of 3.3 V (±5%).
• Industrial temperature version available
Multiplier and Zero Delay Buffer
Description Features
ICS570B
The ICS570B is a high performance Zero Delay Buffer
(ZDB) which integrates ICS’ proprietary analog/digital
Phase Locked Loop (PLL) techniques. The ICS570B,
part of ICS’ ClockBlocks™ family, was designed as a
performance upgrade to meet today’s higher speed and
lower voltage requirements. The zero delay feature
means that the rising edge of the input clock aligns with
the rising edges of both outputs, giving the appearance
of no delay through the device. There are two outputs on
the chip, one being a low-skew divide by two of the other.
The device incorporates an all-chip power down/tri-state
mode that stops the internal PLL and puts both outputs
into a high impedance state.
The ICS570B is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay
through other devices.
The ICS570B was done to improve input to output jitter
from the original ICS570M and ICS570A verisons, and is
recommended for all new 3.3 V only designs.
For 5V applications, use the ICS570A.
• Packaged in 8 pin SOIC.
• Pin-for-pin replacement and upgrade to
ICS570/ICS570A
• Functional equivalent to AV9170 (not a pin for-pin replacement).
• Low input to output skew of 300 ps max (>60 MHz
Block Diagram
ICLK
S1, S0
FBIN
MDS 570B A 1 Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
2
divide by N
External feedback can come from CLK or CLK/2 (see table on page 2).
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
÷2
Output
Buffer
Output
Buffer
CLK
CLK/2
PRELIMINARY INFORMATION
Multiplier and Zero Delay Buffer
ICS570B
Pin Assignment
VDD
GND
ICLK
Clock Multiplier Decoding Table
(Multiplies input clock by shown amount)
S1 S0 CLK CLK/2 CLK CLK/2 FB from CLK/2 * FB from CLK/2 *
#1 #6 pin # 7 pin # 8 pin # 7 pin # 8 (3.3V, MHz) (3.3V, MHz)
0 0
0 M x3 x1.5 x6 x3 2.5 to 25 3 to 25
0 1 x4 x2 x8 x4 2.5 to 19 2.5 to 19
M 0 x8 x4 x16 x8 2.5 to 9.5 2.5 to 9.5
M M x6 x3 x12 x6 2.5 to 12.5 2.5 to 12.5
M 1 x10 x5 x20 x10 2.5 to 7.5 2.5 to 7.5
1 0 x1 ÷2 x2 x1 5 to 75 8 to 75
1 M x16 x8 x32 x16 2.5 to 5 2.5 to 5
1 1 x2 x1 x4 x2 2.5 to 37.5 4.5 to 37.5
0 = connect directly to ground.
M = leave unconnected (self-biases to VDD/2).
1 = connect directly to VDD.
*Input range with CLK feedback is double that for CLK/2.
1 8
S1
2
3
4
8 pin 150 mil SOIC
CLK/2
7
CLK
6
S0
5
FBIN
25°C ICLK Input Range 85°C ICLK Input Range
- -
Pin Descriptions
Number Name Type Description
1 S1 I Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
2 VDD P Connect to +3.3V.
3 GND P Connect to ground.
4 ICLK CI Reference clock input.
5 FBIN CI Feedback clock input.
6 S0 I Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
7 CLK O Clock output per table above.
8 CLK/2 O Clock output per table above. Low skew divide by two of pin 7 clock.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS570B requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS570B to minimize lead inductance. No external power supply filtering is required for this
device. A 27 Ω series terminating resistor can be used next to each output pin.
MDS 570B A 2 Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com