ICST ICS543M, ICS543MT Datasheet
PRELIMINARY INFORMATION
ICS543
ICRO
C
LOCK
Description
The ICS543 is a cost effective way to produce a
high quality clock output divided from a clock
input. The chip accepts a clock input up to
90 MHz at 5.0 V, and by using proprietary Phase
Locked Loop (PLL) techniques, produces a divide
by 3, 5, 6, or 10, or a multiply by 2 of the input
clock. There are two outputs on the chip, one
being a low-skew divide by two of the other. So,
for instance, if an 81 MHz input clock is used, the
ICS543 can produce low skew 27 MHz and
13.5 MHz clocks. The chip has an all-chip power
down mode that stops the outputs low, and an OE
pin that tri-states the outputs.
The ICS543 is a member of the ICS
ClockBlocks™ family of clock building blocks.
See the ICS541 and ICS542 for other clock
dividers, and the ICS300, 501, 502, and 503 for
clock multipliers.
Clock Divider and 2X Multiplier
Features
• Packaged in 8 pin SOIC
• Low cost clock divider and 2X multiplier
• Low skew (500ps) outputs. One is ÷ 2 of other.
• Easy to use with other generators and buffers
• Input clock frequency up to 90 MHz at 5 V
• Output clock duty cycle of 45/55
• Power Down turns off chip
• Output Enable
• Full CMOS clock swings with 25 mA drive
capability at TTL levels
• Advanced, low power CMOS process
• Operating voltages of 3.0 to 5.5 V
Block Diagram
S1, S0
Input Clock
VDD GND
2
Divider and
Selection
Circuitry
Output
Buffer
÷2
Output
Buffer
OE (both outputs)
CLK
CLK/2
MDS 543 A 1 Revision 010599 Printed 12/4/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
PRELIMINARY INFORMATION
Power Down All
ICS543
Clock Divider and 2X Multiplier
Clock Decoding Table
S1 S0 CLK CLK/2 Max. Input Max. Input
#5 #4 pin #8 pin #7 at 5V at 3.3V
0 0
0 1 Input x 2 Input 67 MHz 50 MHz
1 0 Input/5 Input/10 60 MHz 40 MHz
1 1 Input/3 Input/6 90 MHz 60 MHz
0 = connect directly to ground.
1 = connect directly to VDD.
Pin Assignment
ICLK
VDD
GND
S0
1 8
2
3
4
8 pin SOIC
ICRO
7
6
5
C
LOCK
CLK
CLK/2
OE
S1
Pin Descriptions
Number Name Type Description
1 ICLK CI Clock input.
2 VDD P Connect to +3.3V or +5V.
3 GND P Connect to ground.
4 S0 I Select 0 for output clock. Connect to GND or VDD, per decoding table above.
5 S1 I Select 1 for output clock. Connect to GND or VDD, per decoding table above.
6 OE I Output Enable. Tri-states both output clocks when low.
7 CLK/2 O Clock output per Table above. Low skew divide by two of pin 8 clock.
8 CLK O Clock output per Table above.
- -
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS543 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must
be connected close to the ICS543 to minimize lead inductance. No external power supply filtering is
required for this device. A 33 Ω terminating resistor can be used next to each output pin. If a 3.3 V input
clock is applied to the ICLK pin, with the ICS543 at 5 V, the clock must be AC coupled.
MDS 543 A 2 Revision 010599 Printed 12/4/00
Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax
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