ICST ICS513M, ICS513MT Datasheet
ICS513
LOCO™ PLL Clock Generator
Description
The ICS513 LOCO™ is the most cost effective
way to generate a high quality, high frequency
clock output from a 14.31818 MHz crystal or
clock input. The name LOCO stands for LOw
Cost Oscillator, as it is designed to replace crystal
oscillators in many electronic systems. Using
Phase-Locked-Loop (PLL) techniques, the device
uses a standard, inexpensive crystal to produce
output clocks up to 100 MHz.
Stored in the chip’s ROM is the ability to generate
5 different output frequencies, allowing one chip
to work in different speed processor systems.
The device also has a power down mode that turns
off the clock outputs when both select pins are low.
In this mode, the internal PLL is not running.
Block Diagram
Features
• Packaged as 8 pin SOIC
• ICS’ lowest cost PLL clock plus reference
• Produces common computer frequencies
• Input crystal frequency typically 14.3182 MHz
• Output clock frequencies up to 100 MHz
• Low jitter - 40 ps one sigma
• Compatible with all popular CPUs
• Duty cycle of 45/55
• Custom frequencies available
• Operating voltages of 3.0 to 5.5 V
• Power down mode turns off chip
• 25mA drive capability at TTL levels
• Advanced, low power CMOS process
S1, S0
14.31818 MHz
crystal
or clock
X1/ICLK
X2
VDD GND
2
Crystal
Oscillator
Optional crystal capacitors
PLL
Clock
Synthesis
and Control
Circuitry
Output
Buffer
Output
Buffer
CLK
REF
MDS 513 B 1 Revision 080699 Printed 12/4/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA• 95126 • (408)295-9800tel• (408)295-9818fax
ICS513
LOCO™ PLL Clock Generator
Pin Assignment
X1/ICLK
VDD
GND
REF
1 8
2
3
4
X2
7
S1
6
S0
5
CLK
14.31818MHz Crystal or Clock Input
S1 S0 CLK Multiplier Accuracy
0 0 Power Down CLK - -
0 1 100 6.984 1 ppm
M 0 24 1.676 1 ppm
M 1 14.31818 1 0 ppm
1 0 48 3.353 0.017%
1 1 3.6864 0.2576 0.044%
0 = connect directly to ground.
1 = connect directly to VDD.
M = leave unconnected (floating).
CLK and REF stop low in power down state.
Pin Descriptions
Number Name Type Description
1 X1/ICLK I Crystal connection to 14.31818 MHz crystal or clock input.
2 VDD P Connect to +3.3 V or +5 V.
3 GND P Connect to ground.
4 REF O Reference 14.31818 MHz crystal oscillator buffered clock output.
5 CLK O Clock output per table above.
6 S0 TI Select 0 for output clock. Connect to GND or VDD or float. See table above.
7 S1 TI Select 1 for output clock. Connect to GND or VDD or float. See table above.
8 X2 O Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.
Clock Decoding Table (MHz) with
Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection
Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low.
The crystal oscillator and REF output are still active.
2. With a clock input, the phase relationship between the input and output clocks can change
each time the device is powered on.
If a fixed phase relationship is required, please use our ICS571 or other zero delay multiplier.
MDS 513 B 2 Revision 080699 Printed 12/4/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA• 95126 • (408)295-9800tel• (408)295-9818fax
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