ICST ICS1572M-101, ICS1572M-301 Datasheet
Integrated
ICS157 2
Circuit
Systems, Inc.
User Programmable Differential Output Graphics Clock Generator
Description
The ICS1572 is a high performance monolithic phase-locked
loop (PLL) frequency synthesizer. Utilizing ICS’s advanced
CMOS mixed-mode technology, the ICS1572 provide s a low
cost solution for high-end video clock generation in workstations and high-e nd PC applicat ion s.
The ICS1572 has differential video clock outputs (CLK+ and
CLK-) that are compat ible with industry standard vide o DACs.
Another clo ck output , LOAD, is p rovi de d wh ose frequency is
derived from the main clock by a programmable divider. An
additional clock output is available, LD/N2, which is derived
from the LOAD frequency and whose modulus may also be
programmed.
Operati ng frequenc ies are fully progra mmable with direct con trol provi ded for refe rence div ider , pre-scale r, fee dback divi der
and post-sca ler.
Reset of the pipeline delay on Brooktree RAMDACs may
be performed under register control. Outputs may also be set
to desired states to facilitate circuit board testing.
XTAL1
XTAL2
EXTFBK
BLANK
CRYSTAL
OSCILLATOR
(-301 only)
PROGRAMMIN G
INTERFACE
/ R
PHASE-
FREQUENCY
DETECTOR
MUX
/ 2
/ 4
MUX
CHARGE
PUMP
/ M
FILTER
/ N1
Features
• Supports high-resolution graphics - CLK output to
180 MHz
Eliminate s nee d for mul tiple ECL o utput cr ysta l osci lla tors
•
• Fully programmable synthesizer capability - not just a
cloc k mu ltiplier
• Available in 20-pin 300 -m il wi de body SOIC package
• Available in both parallel (101) and serial (301)
programming versions
• Circuit incl uded for reset of Brooktr ee RAMDAC pipeline
delay
Applications
• Workstations
• AutoCad Accelerators
• High-end PC graphics syst ems
ICS1572-101 Pinout
LOOP
VCO
PRESCALER
/ A
FEEDBACK DIVIDER
DIFF.
OUTPUT
MUX DRIVER
/ N2
DRIVER
CLK+
CLK−
LOAD
LD/N2
N.C. 1 20 N.C.
AD0 2 19 AD1
XTAL1 3 18 AD2
XTAL2 4 17 VDD
STROBE 5 16 VDD
VSS 6 15 VDDO
VSS 7 14 IPRG
LOAD 8 13 CLK+
LD/N2 9 12 CLK-
N.C. 10 11 N.C.
ICS1572-301 Pinout
N.C. 1 20 N.C.
AD0 2 19 AD1
XTAL1 3 18 AD2
XTAL2 4 17 VDD
STROBE 5 16 VDD
VSS 6 15 VDDO
VSS 7 14 IPRG
LOAD 8 13 CLK+
LD/N2 9 12 CLK-
N.C. 10 11 N.C.
ICS1572RevC093094
Figure 1
RAMDAC is a trademark of Brooktree Corporation.
ICS1572
Overview
The ICS1572 is ideally suited to provide the graphics system
clock signals required by high-performance video DACs.
Fully pr ogra m mab le fe ed ba ck an d r ef er en ce di vi der c ap abil it y
allow virtually any frequency to be generated, not just simple
multiples of the reference frequency. The ICS1572 uses the
latest genera tion of fre quency synthesis techni ques developed
by ICS and is completely suitable for the most demanding
video applic at io n s.
PLL Synthesizer Description Ratiometric Mode
The ICS1572 generates its output frequencies using phaselocked loop techniques. The phase-locked loop (or PLL) is a
closed-loop feedback system that drives the output frequency
to be ratiometrically related to the reference frequency provided to the PLL (see Figure 1). The reference frequency is
generated by an on-chip crystal oscillator or the reference
frequency may be applied to the ICS1572 from an external
frequency source.
The phase-frequency detector shown in the block diagram
drives the voltage-c ontrolled o scillator , or VCO, to a freq uency
that will cause the two inputs to the phase-frequency detector
to be matc hed in fre que ncy and pha se. This oc curs whe n:
PLL Post-Scaler
A p rogrammable po st-scaler may be inserted b etween the VCO
and the CLK+ a nd CLK- outputs of the ICS1572. T his is useful
in generating of lower frequencies, as the VCO has been
optimize d for hig h-fr eq ue nc y ope ra tion.
The post-scaler allows the selection of:
• VCO frequenc y
• VCO frequenc y di vided by 2
• VCO frequenc y di vided by 4
• Internal regi ster bit (AUXCL K) va lu e
Load Clock Divider
The ICS1572 has an additional programmable divider
(referred to in Figure 1 as the N1 divider) that is used to
generate the LOAD clock frequency for the video DAC. The
modulus of th is div ide r m a y be set to 3, 4, 5, 6, 8, or 10 un de r
register control. The design of this divider permits the output
duty factor t o be 50/50, even when an odd mod ulus is selecte d.
The input frequency to this divider is the output of the PLL
post-scaler described above.
F(
VCO)
This expression is exact; that is, the accuracy of the output
frequen cy depe nds solel y on the re fere nce freq uenc y provi de d
to the part (assuming correctly programmed dividers).
The VCO gain is programmable, which permits the ICS1572 to
be optimized for best performance at all operating frequencies.
The reference divider may be programmed for any modulus
from 1 to 128 in steps of one.
The feedback divider may be programmed for any modulus
from 37 through 391 in ste ps of one . Any e ve n modul us from
392 through 782 can also be achieved by setting the “double”
bit whic h double s the feed back divid er m odulus. The fe edba ck
divider makes use of a dual-modulus prescaler technique that
allows the programmable counters to operate at low speed
without sacrificing resolution. This is an improvement over
conventional fixed prescaler architectures that typically impose a factor-of- four penal ty (or lar ger) in this respect .
T able 1 permits the derivat ion of “A” & “M” count er progra mming dire c tl y fr o m de sired mod ulu s.
F(XTAL1) . Feed back Divider
: =
Refe rence Divider
Digital Inputs - ICS1572-101 Option
The AD0-AD3 pins and the STROBE pin are used to load all
control regi ste rs of t he ICS1572 (-101 option). The AD0-A D3
and STROBE pins are each equipped with a pull-up and will
be at a logic HIGH level when not connected. They may be
driven with sta nda rd TTL or CMOS logic fam il ies.
The address of the register to be loaded is latched from the
AD0-AD3 pins by a negative edge on the STROBE pin. The
data for that register is latched from the AD0-AD3 pins by a
positive edge on the STROBE pin. See Figure 2 for a timing
diagram. Aft e r power-up, th e ICS1572-101 requires 32 regis-
ter writes for new programming to become effective. Since
only 13 re gisters are used at present, the program m ing system
can perform 19 “dummy” writes to address 13 or 14 to comple te th e s eq uence.
2
ICS157 2
This allows the synthesizer to be comple tel y progr am m e d for
the desired frequency before it is made active. Once the part
has been “unlo ck ed ” by the 32 wri tes, progr am m in g beco me s
effe ct ive imme di at e ly.
ALL registers identified in the data sheet (0-9, 11, 12 & 15)
MUST be written upon initial progra mming. The programming
registers are not initialized upon power-up, but the latched
outputs of those registers are. The latch is made transparent
after 32 re gister wr ites. If any register ha s not been wri tten, the
state up on power- up (random ) will be come ef fective . Registe rs
13 & 14 physically do not exist. Regi ste r 10 doe s exi st, but is
reserved for future expansion. To insure compatibility with
possible futur e modific ations to the database, ICS recom mends
that all three unused loc ati ons be writte n with ze ro.
ICS1572-101 Register Loading
STROBE
1
AD0-AD3
5
2
3
DATA VALIDADDRESS VALID
4
Figure 2
An additional control pin on the ICS1572-301, BLANK can
perform either of two functions. It may be used to disable the
phase-fre qu ency detect or in line -l ocke d appli cat ions. Alt erna tively, the BLANK pin may be used as a synchronous enable
for VRAM shift clock genera tion. See sections on Line -Locked
Operations and VRAM shif t clock gen er atio n for deta ils.
Output Description
The differential output drivers, CLK+ and CLK, are currentmode and are designed to drive resistive terminations in a
comple mentary fashion. The outputs are current-sinking only,
with the amount of sink current programmable via the IPRG
pin. Th e sink c urren t, which is steere d to eit her CLK + or CL K-,
is approximately four times the current supplied to the IPRG
pin. For mo st applica tions, a re sistor from VDDO to IPRG wi ll
set the current to the necessary precision. See Figure 6 for
output characteristic s.
The LOAD output is a high-current CMOS type drive whose
frequen cy is controlled by a programmable di vider that may be
selected for a modulus of 3, 4, 5, 6, 8, or 10. It may also be
suppressed under re gi ste r cont rol .
The LD/N2 output is high-current CMOS type drive whose
frequen cy is derive d from the L OAD output . The progr amma ble modulus m ay range from 1 to 512 in steps of on e.
Digital Inputs - ICS1572-301 Option
The programming of the ICS1572-301 is performed serially
by using the DATCLK, DATA, and HOLD~pins to load an
internal shift register.
DATA is shifted into the register on the rising edge of
DATCLK. T he log ic value on the HOL D~ pin i s latc he d at the
same time. When HOLD~ is low, the shift register may be
loaded witho ut di sturbing the op eratio n of the ICS1572. When
high, the shift register outputs are transferred to the control
registers, and the new programming information becomes active. Ordina rily, a high level should be place d on the HOLD~
pin when the last data bit is presented. See Figure 3 for the
program mi ng se que nc e .
ICS1572-301 Register Loading
8
DATCLK
67
DATA
HOLD
DATA_1 DATA_2 DATA_56
Figure 3
Pipeline Delay Reset Function
The ICS1572 implements the clocking sequence required to
reset the pipeline delay on Brooktree RAMDACs. This sequence can be generated by setting the appropriate register bit
(DACRST) to a logic 1 and then resetting to logic 0.
When changing frequencies, it is advisable to allow 500 microseconds after the new frequency is selected to activate the
reset function. The output fr equency of the sy nthesiz e r should
be stable enough at that point for the video DAC to correctly
execute its reset sequence. See Figure 4 for a diagram of the
pipeline delay reset sequence.
Pipeline Delay Reset Timing
STROBE
or
DATCLK
CLK+
LOAD
10
9
T
CLK
11
12
Figure 4
3
ICS1572
Reference Oscillator and Crystal
Selection
The ICS1572 has circuitry on-board to implement a Pierce
oscilla tor with the ad dit ion of only one extern al component, a
quartz crystal. Pierce oscillators operate the crystal in anti(also called parallel-) resonant mode. See the AC Characteristics for the effective capacitive loading to specify when
orde ri n g cr ystal s .
Series-resonant crystals may also be used with the ICS1572.
Be aware that the oscillation frequency wil l be slight ly higher
than the frequency that is stamped on the can (typically 0.025-
0.05%).
As t he e nt ire op erat io n o f the ph ase -lo ck ed l oop d epen ds on
havin g a st able re ferenc e freq uency, we rec ommend that the
crystal be mo unted as c losel y as p ossibl e to the pa cka ge. Avoid
routing digital signals or the ICS1572 outputs underneath or
near these traces. It is also desirable to ground the crystal can
to the ground plane, if possible.
If an exte rnal re fere nce fr eque ncy sour ce is to be used wit h the
ICS1572, it is important that it be jitter-free. The rising and
falling edges of that signa l shou ld be f ast and f re e of n oise fo r
best result s.
ICS1572-101 The ICS1572-101 supports phase detector
disable via a special control mode. When the
PDRSTEN (phase dete ctor rese t enable) bit is
set, a high level on AD3 will disable PLL
locking.
ICS1572-301 The ICS1572-301 supports phase detector
disable via the BLANK pin. When the
PDRSTEN bit is set, a high level on the
BLANK input will disa ble PL L locking.
External Feedback Operation
The ICS1572-301 option also supports the inclusion of an
extern al co unter as the feed back divide r o f the PL L. This m ode
is useful in graphic systems that must be “genlocked” to
external video sourc es.
When the EXT FBE N bi t is set to logi c 1, the ph ase -fr eq ue ncy
detector will use the EXTFBK pin as its feedback input. The
loop phase will be locked to the rising edges of the signal
applied to the EXT FBK i nput .
VRAM Shift Clock Generation
The loop phase is locked to the falling edges of the XTAL1
input signals.
Line-Locked Operation
The ICS1572 supports line-locked clock applications by allowing the LOAD (N1) and N2 divider chains to act as the
feedba c k div ide r fo r the PL L.
The N1 and N2 d ivide r cha ins allow a much l arg er modul us to
be achieved than the PLL ’ s own feedback divide r. Additionall y,
the output of the N2 counter is ac cessible off-c hip for perfo rming horizontal reset of the graphics system, where necessary.
This mode is set under register control (ALTLOOP bit). The
refere nc e di vid er (R counter) i s set to di vid e by 1 in this m ode ,
and the HSYNC signal of the external video will be supplied
to the XTAL1 input. The output frequency of the synthesizer
wil l t h en be:
F
: = F (XTAL1) . N1 . N2.
(CLK)
By using the phase-detector hardware disable mode, the PLL
can be ma de to fre e- run a t the be gin ning o f the v er tica l i n t e r v a l
of the external video, and ca n be reactivated at its com ple tion.
The ICS1572-301 option supports VRAM shift clock generation and interruption. B y programmin g the N2 c ounter to d ivide
by 1, the LD/N2 output becomes a duplicate of the LOAD
output. When the SCEN bit is set, the LD/N2 output may be
synchronously started and stopped via the blank pin. When
BLANK is high, the LD/ N2 wil l be free -run ning and in phase
with LOAD. When BLANK is take n low , the LD/N2 out put is
stopped at a low level. See Figure 5 for a diagram of the
sequence. Note that this use of the BLANK pin precludes its use
for phase comparator disable (see Line-Locked O peration).
VRAM Shift Clock Control
BLANK
LOAD
LD/N2
Figure 5
4
ICS157 2
Power-On Initialization
The ICS1572 has an internal power-on reset circuit that performs the followin g func t ion s:
1) Sets the mu lt ipl e xe r to pass the re ferenc e fr equenc y
to the CLK+ and CL K- outputs.
2) Selects the mo dul us of the N1 di vid er (for the
LOAD clock) to be four .
These functions should allow initialization of most graphics
systems that can not imme diately provide fo r register pro gramming upon system power-up.
Because the power -o n reset circ uit is on the VDD supply, and
because that supply is filte red, ca re must be take n to allow the
reset to de-assert before programming. A safe guideline is to
allow 20 microse c onds a fter t he VDD supp ly reac he s 4 vol ts.
Programming Notes
• VCO Frequency Range: Use the post-divider to keep the
VCO frequency as high as possible within its operating
range.
• Divider Range: For best results in normal situatio ns (i.e.,
pixel cloc k ge nera tion for hi-res displ ay s), kee p the refe rence di vide r m odulu s as short a s p ossibl e (f or a fre que ncy
at the output of the reference divider in the few hundred
kHz to several MHz range) . If you need to go to a lower
phase comparator reference frequency (usually required
for increa sed frequ ency accura cy), that is acceptab le, but
jitter perfo rman ce wil l suffer some wha t.
• VCO Gain Programming: Use the minimum gain which
can relia bly achi eve t he VCO fre quen cy desi red, as shown
here:
VCO GAIN MAX FREQUENCY
4 120 MHz
5 200 MHz
6 230 MHz
7*
* SPECIAL APPLICATION. Contact factory for custom product above
230 MHz.
• Phase Detector Gain: For most graph ics appl ica tions and
divider ranges, set P[1,0] = 10 and set P[2] = 1. Under
some circumstances, setting the P[2] bit “on” can reduce
jitter. During 1572 operation at exact multiples of the
crystal frequency, P[2] bit = 0 may provide the best jitter
performance.
Board Test Support
It is often desi rabl e to statica lly contr ol the leve ls of the output
pins for ci rc ui t b oa rd t e st . T he ICS1572 supports this through
a register programmable mode, AUXEN. When this mode is
set, two register bits directly control the logic levels of the
CLK+/CLK- pins and the LOAD pin. This mode is activated
when the S[0] and S[1] bits are both set to logi c 1. See Registe r
Mapping for deta il s.
Power Supplies and Decoupling
The ICS1572 has two VSS pins to reduc e the effe cts of package
inductance. Both pins are connected to the same potential on
the die (the ground bus). BOTH of these pins should connect
to the ground plan e of the video board a s close to the package
as is po ssible.
The ICS1572 has a VDDO pin which is the supply of +5 volt
power to all output drive rs. This pin should be connect ed to the
power plane (or bus) using standard high-frequency decoupling pra ctice. T hat is, ca pacitors should hav e low seri es induc tance an d be mounte d c lo se to the ICS1572.
The VDD pin is the power suppl y pin for the PLL synthesizer
circuitry and ot her lower c urrent digital functions. We recom mend that RC decoupling or zener regulation be provided for
this pin (as sh own in the recommen ded application ci rcuitry).
This wil l allow the PLL to “t rack” through power supply
fluctuations without visible effects. See Figure 7 for typical
external circui try.
Figure 6
5
ICS1572
ICS1572 Typical Interface
DATA BUS
SELECT
1 N.C. N.C 20
2AD0 AD1 19
3XTAL1 AD2 18
4XTAL2 AD3 17
5 STROBE VDD 16
6 VSS VDDO 15
7 VSS IPRG 14
8LOAD CLK+ 13
9 LD/N2 CLK- 12
10 N.C. N.C. 11
Figure 3
+5V
+
120
120
390390
TO
RAMDAC
6
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