ICST AV9250F-29-T, ICS9250F-29-T Datasheet
Integrated
Circuit
Systems, Inc.
ICS9250-29
Third party brands and names are the property of their respective owners.
Block Diagram
9250-29 Rev A 02/01/01
Recommended Application:
Solano type chipset.
Output Features:
• 2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
• 13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
• 5 PCI (3.3 V) @33.3MHz
• 1 IOAPIC (2.5V) @ 33.3 MHz
• 3 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 (3.3V) @ 48 MHz (Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation,
0 to -0.5% down spread.
•I
2
C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
** This input has a 50KW pull-up to VDD
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
X2
GNDR
VDD3
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
SCLK
S DATA
GNDF
VDDF
48MHz_0
GNDL
VDDL
CPUCLK0
CPUCLK1
GND1
SDRAM0
SDRAM1
VDD1
GND1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD1
GND1
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD1
GND1
SDRAM10
SDRAM11
VDD1
GND1
SDRAM12
TRISTATE#/PD#**
48MHz_1
ICS9250-29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
REF
CPU66/100/133 [1:0]
VDDL
3V66 [2:0]
SDRAM [12:0]
PCICLK [4:0]
IOAPIC
VDDL
PLL2
48MHz [1:0]
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS(1:0)
PD#
TRISTATE#
2
2
3
13
5
/2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
#etatsirT0SF1SF
UPC
zHM
MARDS
zHM
00X etatsirTetatsirT
01XtseTtseT
100 zHM66zHM001
110 zHM001zHM001
101 zHM331zHM331
111 zHM331zHM001
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
Power Groups
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
VDD2, GND2 = PCI (digital)
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
2
ICS9250-29
The ICS9250-29 is a single chip clock solution for Solano type chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-29
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
General Description
Pin Configuration
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1CIPAOITUO.zHM3.33tagninnurtuptuokcolcV5.2
55,2LDDVRWPCIPAOI&UPCrofylppusrewopV5.2
65,3LDNGRWPCIPAOI&UPCrofylppusrewopV5.2rofdnuorG
4
1SFNIytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF
FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
,72,32,71,9,5
94,34,73,33
xDDVRWPylppusrewopV3.3
61XNI
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
72XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
,62,22,81,31,8
25,84,24,63,23
xDNGRWPylppusV3.3rofsnipdnuorG
01,11,21)0:2(66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3
120SFNI.ytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF
41,51,61,91,02)0:4(KLCICPTUOstuptuokcolcICPV3.3
03
#ETATSIRTNI
#ETATSIRTehtotstluafednip#DP/#ETATSIRTehtpurewoptA
derahSees(.sedomTSETdna#ETATSIRTehtelbaneotnoitcnuftupni
.)noitpircsedllufrofnoitarepOniP
#DPNI
otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola
ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht
.sm3nahtretaerg
42KLCSNIIfotupnikcolC
2
tupniC
52ATADSNIIroftupniataD
2
.tupnilairesC
82,92)0:1(zHM84TUO.stuptuokcolczHM84dexiFV3.3
,83,53,43,13
,44,14,04,93
15,05,74,64,54
MARDS
]0:21[
TUO
nacstuptuoMARDSllA.zHM331dnazHM001gninnurtuptuoV3.3
Ihguorhtffodenruteb
2
C
45,35)0:1(KLCUPCTUO
gnidnepedzHM331rozHM001,zHM66.tuptuokcolcsubtsoHV5.2
.snipSFno
3
ICS9250-29
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the
output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOI66V3KLCICP
,FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONO
onaloS
noitidnoC
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V526.2=2qddV
DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV3.3xaM
,sdaolpacetercsidxaM
V564.3=3qddV
DNGro3qddV=stupnicitatsllA
edoMnwodrewoP
)0=#NWDRWP(
Am2Am2
zHM66evitcAlluF
00=)0:1(SF
Am53Am044
zHM001evitcAlluF
10=)0:1(SF
Am05Am034
zHM331evitcAlluF
11=)0:1(SF
Am06Am044
zHM331evitcAlluF
01=)0:1(SF
Am06Am005
4
ICS9250-29
1. The ICS clock generator is a slave/receiver, I2C (SMB) component. It is only a "write" mode SMB device, no readback on
this part. Read-Back will lock up the PIIX-4 due to the Byte count of 00
H
.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The
data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0) through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
A
CK
Byte 0
A
CK
Byte 1
ACK
Byte 2
A
CK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
A
CK
Stop Bit
How to Write:
Note: This clock does not support Read Back. Doing a
read back will lock up the PIIX-4 system.
5
ICS9250-29
etatsirT0SF1SFUPCMARDS66V3ICPzHM84FERCIPAOI
00X etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
01X 2/KLCT2/KLCT3/KLCT6/KLCT2/KLCTKLCT6/KLCT
100 zHM6.66zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
110 zHM001zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
101 zHM331zHM331zHM6.66zHM3.33zHM84zHM813.41zHM3.33
111 zHM331zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
Truth Table
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- )DIdevreseR(0)evitcanI/evitcA(
6tiB- )DIdevreseR(0)evitcanI/evitcA(
5tiB- )DIdevreseR(0)evitcanI/evitcA(
4tiB- )DIdevreseR(1)evitcanI/evitcA(
3tiB- murtcepSdaerpS0)ffO=0/nO=1(
2tiB921_zHM841)evitcanI/evitcA(
1tiB820_zHM841)evitcanI/evitcA(
0tiB- )DIdevreseR(0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB047MARDS1)evitcanI/evitcA(
6tiB146MARDS1)evitcanI/evitcA(
5tiB445MARDS1)evitcanI/evitcA(
4tiB544MARDS1)evitcanI/evitcA(
3tiB643MARDS1)evitcanI/evitcA(
2tiB742MARDS1)evitcanI/evitcA(
1tiB051MARDS1)evitcanI/evitcA(
0tiB150MARDS1)evitcanI/evitcA(
Note:
Reserved ID bits must be written with "0"
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