ICST AV9250F-28-T, ICS9250F-28-T Datasheet
Integrated
Circuit
Systems, Inc.
ICS9250-28
Third party brands and names are the property of their respective owners.
Block Diagram
9250-28 Rev B 10/26/00
Recommended Application:
810/810E and 815 type chipset.
Output Features:
• 2 CPU (2.5V) (up to 133MHz achievable through I
2
C)
• 13 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
• 2 PCI (3.3 V) @33.3MHz
• 1 IOAPIC (2.5V) @ 33.3 MHz
• 3 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 (3.3V) @ 48 MHz (Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation,
0 to -0.5% down spread.
•I
2
C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
IOAPIC
VDDL
GND
*FS1/REF0
VDDREF
X1
X2
GND
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
FS0
GND
VDDA
PD#
SCLK
S DATA
GND
VDD48
48MHz_0
48MHz_1
FS2
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
ICS9250-28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
2SF0SF1SFnoitcnuF
00X etatsirT
01XtseT
100
zHM66=UPCevitcA
zHM001=MARDS
110
zHM001=UPCevitcA
zHM001=MARDS
101
zHM331=UPCevitcA
zHM331=MARDS
111
zHM331=UPCevitcA
zHM001=MARDS
REF0
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
PLL2
48MHz (1:0)
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS(2:0)
PD#
2
2
3
13
2
/2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
2
ICS9250-28
The ICS9250-28 is part of a two chip clock solution for 810/810E and 815 type chipset. Combined with the
ICS9112-17, the ICS9250-28 provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The
ICS9250-28 employs a proprietary closed loop design, which tightly controls the percentage of spreading over
process and temperature variations.
General Description
Pin Configuration
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1CIPAOITUO.zHM3.33tagninnurtuptuokcolcV5.2
65,2LDDVRWPCIPAOI&UPCrofylppusrewopV5.2
4
1SFNIytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF
0FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
,52,02,41,9,5
94,44,04,53,13
DDVRWPylppusrewopV3.3
61XNI
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
72XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
,91,71,31,8,3
,93,43,03,42
55,25,84,34
DNGRWPylppusV3.3rofsnipdnuorG
01,11,21)0:2(66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3
81,82)0,2(SFNI
.ytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF
.3egapnoelbatytilanoitcnuFotreferesaelP
51,61]0:1[KLCICPTUOstuptuokcolcICPV3.3
12#DPNI
otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola
ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht
.sm3nahtretaerg
22KLCSNIIfonipkcolC
2
tnarelotV5yrtiucricC
32ATADSO/IIrofnipataD
2
tnarelotV5yrtiucricC
72,620_zHM84TUO.stuptuokcolczHM84dexiFV3.3
,63,33,23,92
,24,14,83,73
15,05,74,64,54
MARDS
)0:21(
TUO
ffodenrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3
Ihguorht
2
C
35,45)0:1(KLCUPCTUO
gnidnepedzHM331rozHM001,zHM66.tuptuokcolcsubtsoHV5.2
.snip)0:2(SFno
3
ICS92 50-28
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOIzHM66KLCICP
,FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONO
518
noitidnoC
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V526.2=2qddV
DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V564.3=2qddV
DNGro3qddV=stupnicitatsllA
edoMnwodrewoP
0=#NWDRWP(
Am01Am01
zHM66evitcAlluF
010=]0:2[SF
Am07Am004
zHM001evitcAlluF
110=]0:2[SF
Am001Am004
zHM331evitcAlluF
111=]0:2[SF
Am031Am054
4
ICS9250-28
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
2SF0SF1SFUPCMARDS66V3ICPzHM84FERCIPAOI
00X etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
01X 2/KLCT2/KLCT3/KLCT6/KLCT2/KLCTKLCT6/KLCT
100 zHM6.66zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
110 zHM001zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
101 zHM331zHM331zHM6.66zHM3.33zHM84zHM813.41zHM3.33
111 zHM331zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
Truth Table
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the
CPU is at the 133MHz FSB speed as shown in this table. The CPU, 3V66, PCI, and IOAPIC clocks will be glitch
free during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "0".
Note3: Undefined bits can be written either as "1 or 0"
tiBnoitpitcseDDWP
7tiB)2etoN(tibdevreseRSCI 0
6tiB)2etoN(tibdevreseRSCI 0
5tiB)2etoN(tibdevreseRSCI 0
4tiB)2etoN(tibdevreseRSCI 0
3tiB)2etoN(tibdevreseRSCI 0
2tiB)3etoN(tibdenifednU X
1tiB)3etoN(tibdenifednU X
0tiB
0tiB0SF1SF
KLCUPC
zHM
MARDS
zHM
66V3
zHM
KLCICP
zHM
CIPAOI
zHM
0
1etoN
000 66.660.00166.6633.3333.33
010 0.0010.00166.6633.3333.33
001 23.33123.33166.6633.3333.33
011 23.3310.00166.6633.3333.33
100 66.660.00166.6633.3333.33
110 0.0010.00166.6633.3333.33
101 23.33123.33166.6633.3333.33
111 23.33123.33166.6633.3333.33
5
ICS92 50-28
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- DIdevreseR0)evitcanI/evitcA(
6tiB- DIdevreseR0)evitcanI/evitcA(
5tiB- DIdevreseR0)evitcanI/evitcA(
4tiB- DIdevreseR1)evitcanI/evitcA(
3tiB-
murtcepSdaerpS
)ffO=0/nO=1(
1)evitcanI/evitcA(
2tiB721zHM841)evitcanI/evitcA(
1tiB620zHM841)evitcanI/evitcA(
0tiB- DIdevreseR0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB837MARDS1)evitcanI/evitcA(
6tiB146MARDS1)evitcanI/evitcA(
5tiB245MARDS1)evitcanI/evitcA(
4tiB544MARDS1)evitcanI/evitcA(
3tiB643MARDS1)evitcanI/evitcA(
2tiB742MARDS1)evitcanI/evitcA(
1tiB051MARDS1)evitcanI/evitcA(
0tiB150MARDS1)evitcanI/evitcA(
Note: Reserved ID bits must be written as "0"
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
tiB#niPemaNDWPnoitpircseD
7tiB21)PGA(2-66V31)evitcanI/evitcA(
6tiB9221MARDS1)evitcanI/evitcA(
5tiB2311MARDS1)evitcanI/evitcA(
4tiB3301MARDS1)evitcanI/evitcA(
3tiB639MARDS1)evitcanI/evitcA(
2tiB738MARDS1)evitcanI/evitcA(
1tiB611KLCICP1)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
6
ICS9250-28
Group Timing Relationship Table
1
Byte 4: Reserved Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
puorGzHM66UPC
zHM001MARDS
zHM001UPC
zHM001MARDS
zHM331UPC
zHM001MARDS
zHM331UPC
zHM331MARDS
tesffOecnareloTtesffOecnareloTtesffOecnareloTtesffOecnareloT
MARDSotUPCsn5.2-sp005sn0.5sp005sn0.0sp005sn57.3sp005
66V3otUPCsn5.7sp005sn0.5sp005sn0.0sp005sn0.0sp005
66V3otMARDSsn0.0sp005sn0.0sp005sn0.0sp005sn57.3-sp005
ICPot66V3sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005sn5.3-5.1sp005
ICPotICPsn0.0sp005sn0.0sp005sp005sn0.1sn0.0sp005
TOD&BSUhcnysAA/NhcnysAA/NhcnysAA/NhcnysAA/N
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