ICST AV9250F-27-T, ICS9250F-27-T Datasheet
Integrated
Circuit
Systems, Inc.
ICS9250-27
Third party brands and names are the property of their respective owners.
Block Diagram
9250-27 Rev B 02/15/01
Recommended Application:
810/810E and 815 type chipset.
Output Features:
• 3 CPU (2.5V) (up to 133MHz achievable through I
2
C)
• 9 SDRAM (3.3V) (up to 133MHz achievable
through I
2
C)
• 7 PCI (3.3 V) @33.3MHz
• 2 IOAPIC (2.5V) @ 33.3 MHz
• 3 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 (3.3V) @ 48 MHz (Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation,
0 to -0.5% down spread.
•I
2
C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 50KΩ pull-down to GND.
*FS2//REF0
VDD
X1
X2
GND
GND
3V66-0
3V66-1
3V66-2
VDD
VDD
PCICLK_F
PCICLK0
GND
PCICLK1
PCICLK2
GND
PCICLK3
PCICLK4
PCICLK5
VDD
VDD
GND
GND
48MHz_0
48MHz_1
VDD
FS0
GND
IOAPIC0
IOAPIC1
VDDL
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL
GND
SDRAM0
SDRAM1
VDD
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD
SDRAM6
SDRAM7
GND
SDRAM_F
VDD
PD#
SCLK
S DATA
FS1
ICS9250-27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
2SF1SF0SFnoitcnuF
X00 etatsirT
X0 1tseT
010
zHM66=UPCevitcA
zHM001=MARDS
011
zHM001=UPCevitcA
zHM001=MARDS
110
zHM331=UPCevitcA
zHM331=MARDS
111
zHM331=UPCevitcA
zHM001=MARDS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
REF0
CPU66/100/133 (2:0)
VDDL
3V66 (2:0)
SDRAM (7:0)
PCICLK (5:0)
IOAPIC (1:0)
VDDL
SDRAM_F
PCICLK_F
PLL2
48MHz (1:0)
X1
X2
XTAL
OSC
Control
Logic
Config
Reg
FS (2:0)
PD#
2
3
3
8
6
2
/2
/2
/3
/2
PLL1
Spread
Spectrum
SDATA
SCLK
Power Groups
AVDD = Pin 22 Analog power for PLL
AGND = Pin 23 Analog ground
VDD48 = Pin 27 Analog power for 48MHz PLL
GND = Pin 24 Analog ground for 48MHz PLL
2
ICS9250-27
The ICS9250-27 is a single chip clock solution for 810/810E and 815 type chipset. It provides all necessary clock
signals for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10
dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS925027 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and
temperature variations.
General Description
Pin Configuration
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1
2SFNIytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF
0FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
31XNI
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
42XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
,32,71,41,6,5
,74,14,53,42
65,84
DNGRWPylppusV3.3rofsnipdnuorG
7,8,9)0:2(66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3
,12,11,01,2
44,83,33,72,22
DDVRWPylppusrewopV3.3
21F_KLCICPTUOtuptuokcolcICPV3.3gninnureerF
,61,81,91,02
31,51
)0:5(KLCICPTUOstuptuokcolcICPV3.3
520_zHM84TUOBSUrofstuptuokcolczHM84dexiFV3.3
621_zHM84TUO
oediv/scihpargroftuptuoregnortS.tuptuokcolczHM84dexifV3.3
)etaregdesn/V1muminim(ecafretni
82,92)0:1(SFNI
.ytilanoitcnuftuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF
.3egapnoelbatytilanoitcnuFotreferesaelP
03ATADSO/IIrofnipataD
2
tnarelotV5yrtiucricC
13KLCSNIIfonipkcolC
2
tnarelotV5yrtiucricC
23#DPNI
otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola
ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht
.sm3nahtretaerg
,04,93,73,63
64,54,34,24
)0:7(MARDSTUO
ffodenrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3
Ihguorht
2
C
43F_MARDSTUOIhguorhtffodenrutebtonnac,MARDSzHM001gninnureerfV3.3
2
C
25,05,94)0:2(KLCUPCTUO
gnidnepedzHM331rozHM001,zHM66.tuptuokcolcsubtsoHV5.2
.snipSFno
35,15LDDVRWPCIPAOI&UPCrofylppyusrewopV5.2
55,45)0:1(CIPAOITUO.zHM3.33tagninnurstuptuokcolcV5.2
3
ICS9250-27
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Maximum Allowed Current
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOIzHM66KLCICP
,FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONO
518
noitidnoC
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V526.2=2qddV
DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V564.3=2qddV
DNGro3qddV=stupnicitatsllA
edoMnwodrewoP
0=#NWDRWP(
Am01Am01
zHM66evitcAlluF
010=]0:2[SF
Am07Am082
zHM001evitcAlluF
110=]0:2[SF
Am001Am082
zHM331evitcAlluF
111=]0:2[SF
4
ICS9250-27
2SF1SF0SFUPCMARDS66V3ICPzHM84FERCIPAOI
X00 etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
X0 1 2/KLCT2/KLCT3/KLCT6/KLCT2/KLCTKLCT6/KLCT
010 zHM6.66zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
011 zHM001zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
110 zHM331zHM331zHM6.66zHM3.33zHM84zHM813.41zHM3.33
111 zHM331zHM001zHM6.66zHM3.33zHM84zHM813.41zHM3.33
Truth Table
Byte 0: Control Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiBDIdevreseR0)evitcanI/evitcA(
6tiBDIdevreseR0)evitcanI/evitcA(
5tiBDIdevreseR0)evitcanI/evitcA(
4tiBDIdevreseR0)evitcanI/evitcA(
3tiB
murtcepSdaerpS
)ffO=0/nO=1(
1)evitcanI/evitcA(
2tiB621zHM841)evitcanI/evitcA(
1tiB520zHM841)evitcanI/evitcA(
0tiB942KLCUPC1)evitcanI/evitcA(
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB637MARDS1)evitcanI/evitcA(
6tiB736MARDS1)evitcanI/evitcA(
5tiB935MARDS1)evitcanI/evitcA(
4tiB044MARDS1)evitcanI/evitcA(
3tiB243MARDS1)evitcanI/evitcA(
2tiB342MARDS1)evitcanI/evitcA(
1tiB541MARDS1)evitcanI/evitcA(
0tiB640MARDS1)evitcanI/evitcA(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
5
ICS9250-27
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always with
SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the default 0 to
1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU is at the
133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free during this
transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3: Undefined bits can be written either as "1 or 0"
tiBnoitpitcseDDWP
7tiB)2etoN(tibdevreseRSCI 0
6tiB)2etoN(tibdevreseRSCI 0
5tiB)2etoN(tibdevreseRSCI 0
4tiB)2etoN(tibdevreseRSCI 0
3tiB)2etoN(tibdevreseRSCI 0
2tiB)3etoN(tibdenifednU X
1tiB)3etoN(tibdenifednU X
0tiB
0tiB0SF1SF
KLCUPC
zHM
MARDS
zHM
66V3
zHM
KLCICP
zHM
CIPAOI
zHM
0
1etoN
000 66.660.00166.6633.3333.33
010 0.0010.00166.6633.3333.33
001 23.33123.33166.6633.3333.33
011 23.3310.00166.6633.3333.33
100 66.660.00166.6633.3333.33
110 0.0010.00166.6633.3333.33
10 1 23.33123.33166.6633.3333.33
111 23.33123.33166.6633.3333.33
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
tiB#niPemaNDWPnoitpircseD
7tiB9 )PGA(2-66V31)evitcanI/evitcA(
6tiB025KLCICP1)evitcanI/evitcA(
5tiB914KLCICP1)evitcanI/evitcA(
4tiB813KLCICP1)evitcanI/evitcA(
3tiB612KLCICP1)evitcanI/evitcA(
2tiB511KLCICP1)evitcanI/evitcA(
1tiB310KLCICP1)evitcanI/evitcA(
0tiB- tibdenifednUX)evitcanI/evitcA(
Loading...