Integrated
Circuit
Systems, Inc.
ICS9250-26
Third party brands and names are the property of their respective owners.
Block Diagram
9250-26 Rev B 01/19/01
Recommended Application:
810/810E type chipset. Provides three CPU speeds
(66.6, 100, 133MHz) with SDRAM = 133.3MHz.
Output Features:
• 3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz
achievable through I
2
C)
• 9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz
achievable through I
2
C)
• 8 PCI (3.3 V) @33.3MHz
• 2 IOAPIC (2.5V) @ 33.3 MHz
• 2 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation ,
down spread 0 to -0.5% and ± 0.25% center spread.
•I
2
C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 120KΩ pull-down to GND.
*FS2//REF0
VDD0
X1
X2
GND0
GND1
3V66-0
3V66-1
VDD1
VDD2
PCICLK0
PCICLK1
PCICLK2
GND2
PCICLK3
PCICLK4
GND2
PCICLK5
PCICLK6
PCICLK7
VDD2
VDD3
GND3
GND4
48MHz_0
48MHz_1
VDD4
FS0
GNDL1
IOAPIC0
IOAPIC1
VDDL1
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL0
GND5
SDRAM0
SDRAM1
VDD5
SDRAM2
SDRAM3
GND5
SDRAM4
SDRAM5
VDD5
SDRAM6
SDRAM7
GND5
SDRAM_F
VDD5
PD#
SCLK
S DATA
FS1
ICS9250-26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
2SF1SF0SFnoitcnuF
X00 etatsirT
X0 1tseT
010
zHM66=UPCevitcA
zHM001=MARDS
011
zHM001=UPCevitcA
zHM001=MARDS
111
zHM331=UPCevitcA
zHM001=MARDS
110
)noitidnoClaicepS(
zHM331=UPCevitcA
zHM331=MARDS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9250-26
The ICS9250-26 is a single chip clock solution for 810/810E type chipset. It provides all necessary clock signals for
such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-26 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
General Description
Pin Configuration
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1
2SFTUO
tuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF
05htiw(ytilanoitcnuf Ω)
0FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
31XTUO
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
42XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
,32,42,53,14,74
5,6,41,71
)0:5(DNGRWPylppusV3.3rofsnipdnuorG
7,8]0:1[66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3
,22,72,33,83,44
2,9,01,01,12
)0:5(DDVRWPylppusrewopV3.3
,61,81,91,02
11,21,31,51
)0:7(KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3
52,62)0:1(zHM84TUOBSUrofstuptuokcolczHM84dexiFV3.3
82,92)0:1(SFTUO
tuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF
.3egapnoelbatytilanoitcnuFotreferesaelP.ytilanoitcnuf
03ATADSNIIroftupniataD
2
.tupnilairesC
13KLCSNIIfotupnikcolC
2
tupniC
23#DPNI
ecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
ehtdnadelbasideraskcolclanretniehT.etatsrewopwolaotni
nwodrewopehtfoycnetalehT.deppotseralatsyrcehtdnaOCV
.sm3nahtretaergebtonlliw
,24,04,93,73,63
64,54,34
)0:7(MARDSTUO
denrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3
Ihguorhtffo
2
C
43F_MARDSTUOIybdetceffatonMARDSzHM001gninnureerfV3.3
2
C
84,65)0:1(LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG
94,05,25)0:2(KLCUPCTUO
zHM331zHM001rozHM66.tuptuokcolcsubtsoHV5.2
snipSFnognidneped
35,15)0:1(LDDVRWPCIPAOI&UPCrofylppyusrewopV5.2
55,45)0:1(CIPAOITUO.zHM3.33tagninnurstuptuokcolcV5.2
3
ICS9250-26
Maximum Allowed Current
E018
noitidnoC
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V526.2=2qddV
DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V564.3=2qddV
DNGro3qddV=stupnicitatsllA
edoMnwodrewoP
0=#NWDRWP(
Am01Am01
zHM66evitcAlluF
01=0,1LES
Am07Am082
zHM001evitcAlluF
11=0,1LES
Am001Am082
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOIzHM66KLCICP
,FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONO
Power Groups*
VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66
VDD2, GND2 = PCICLK
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz
VDD5, GND5 = SDRAM_F, SDRAM
VDDL0, GNDL0 = CPUCLK
VDDL1, GNDL1 = IOAPIC
* To ensure the processor will power up to the desired frequency, the 3.3V supply to the ICS9250-26 needs to reach a stable
condition before the 2.5V supply does. In most systems, the power up ramp of the 2.5V is slower than the 3.3V ramp. For those
instances, no special requirements are necessary.
4
ICS9250-26
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
A
CK
Byte 0
A
CK
Byte 1
ACK
Byte 2
A
CK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
A
CK
Stop Bit
How to Write:
5
ICS9250-26
tiBnoitpitcseDDWP
7tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
6tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
5tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
tiB
)0,3(
)0,3(tiB
KLCUPC
zHM
MARDS
zHM
66V3
zHM
KLCICP
zHM
XXXX
1etoN
2SF
)WH(
0SF
)WH(
1LES
)3tiB(
0LES
)0tiB(
0000 76.6600.00106.6603.33
0001 00.0700.50100.0700.53
0010 76.2700.90176.2733.63
0011 76.4700.21166.4733.73
0100 00.00100.00106.6603.33
0101 00.50100.50100.0700.53
0110 00.90100.90176.2733.63
0111 10.21100.21166.4733.73
1000 43.33143.33166.8833.44
1001 00.04100.50100.0700.53
1010 00.02100.0900.0600.03
1011 00.42100.42166.2833.14
1100 43.33100.00106.6603.33
1101 00.05100.05100.5705.73
1110 00.04100.04100.0700.53
1111 99.23199.23106.6603.33
4tiB
%5.-ot0murtcepSdaerpSdaerpSnwoD=0
%52.±murtcepSdaerpSdaerpSretneC=1
0
2tiB)noitarepokcolclamronrof1ebotsdeeN(desutoN 1
1tiB)noitarepokcolclamronrof1ebotsdeeN(desutoN 1
Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2
defining specific frequency.
6
ICS9250-26
Byte 0: Control Register
(1 = enable, 0 = disable)
Byte 1: Control Register
(1 = enable, 0 = disable)
Byte 2: Control Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
tiB#niPemaNDWPnoitpircseD
7tiBDIdevreseR0)evitcanI/evitcA(
6tiBDIdevreseR0)evitcanI/evitcA(
5tiBDIdevreseR0)evitcanI/evitcA(
4tiBDIdevreseR1)evitcanI/evitcA(
3tiB
murtcepSdaerpS
)ffO=0/nO=1(
1)evitcanI/evitcA(
2tiB621zHM841)evitcanI/evitcA(
1tiB520zHM841)evitcanI/evitcA(
0tiB942KLCUPC0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB637MARDS1)evitcanI/evitcA(
6tiB736MARDS1)evitcanI/evitcA(
5tiB935MARDS1)evitcanI/evitcA(
4tiB044MARDS1)evitcanI/evitcA(
3tiB243MARDS1)evitcanI/evitcA(
2tiB342MARDS1)evitcanI/evitcA(
1tiB541MARDS1)evitcanI/evitcA(
0tiB640MARDS1)evitcanI/evitcA(
Note: Do not write in ID bits, these bits are for ICS internal use only.
tiB#niPemaNDWPnoitpircseD
7tiB027KLCICP1)evitcanI/evitcA(
6tiB916KLCICP1)evitcanI/evitcA(
5tiB815KLCICP1)evitcanI/evitcA(
4tiB614KLCICP1)evitcanI/evitcA(
3tiB513KLCICP1)evitcanI/evitcA(
2tiB312KLCICP1)evitcanI/evitcA(
1tiB211KLCICP1)evitcanI/evitcA(
0tiB- devreseR1)evitcanI/evitcA(
Must write a '1' in bit 0 after read back.
7
ICS9250-26
Byte 3: Reserved Register
(1 = enable, 0 = disable)
Byte 4: Reserved Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
tiB#niPemaNDWPnoitpircseD
7tiB- devreseR0)evitcanI/evitcA(
6tiB- devreseR0)evitcanI/evitcA(
5tiB- devreseR0)evitcanI/evitcA(
4tiB- devreseR0)evitcanI/evitcA(
3tiB- devreseR0)evitcanI/evitcA(
2tiB- devreseR0)evitcanI/evitcA(
1tiB- devreseR0)evitcanI/evitcA(
0tiB- devreseR0)evitcanI/evitcA(
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
8
ICS9250-26
Electrical Characteristics - Input/Supply/Common Output Paramete
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PA RAM ETER SYMBOL CONDITIONS M IN TYP M AX UNIT S
Input High Voltage V
IH
2V
DD
+0.3 V
Input Low Voltage V
IL
VSS-0.3 0.8 V
Input High Current I
IH
VIN = V
DD
-5 5
µ
A
I
IL1
VIN = 0 V; Inputs with no pull-up resistors -5 2
I
IL2
VIN = 0 V; Inputs with pull-up resistors -200 -100
C
L
= 0 pF; Select @ 66 MHz 97 110
C
L
= 0 pF; Select @ 100 MHz 91 105
C
L
= 0 pF; Select @ 133 MHz 100 130
C
L
= Max loads; Select @ 66 MHz 275 310
C
L
= Max loads; Select @ 100 MHz 267 300
C
L
= Max loads; Select @ 133 MHz 278 350
C
L
= 0 pF; Select @ 66 MHz 8 10
C
L
= 0 pF; Select @ 100 MHz 11 15
C
L
= 0 pF; Select @ 133 MHz 13 20
C
L
= Max loads; Select @ 66 MHz 22 70
C
L
= Max loads; Select @ 100 MHz 31 100
C
L
= Max loads; Select @ 133 MHz 37 130
I
DD3.3P D
CL = Max loads
220 400
I
DD.25PD
Input address VDD or GND
<1 10
Input Frequency F
i
VDD = 3.3 V 12 14.318 16 MHz
Pin Inductance L
pin
7nH
C
IN
Logic Inputs 5 pF
C
OUT
Output pin capacitance 6 pF
C
INX
X1 & X2 pins 27 45 pF
Transition time
1
T
trans
To 1st crossing of t arget frequency 5 ms
Settling time
1
T
s
From 1st cr ossing to 1% target frequency 5 ms
Clk Stabilization
1
T
STAB
From VDD = 3.3 V to 1% target frequency 5 ms
t
PZH,tPZL
Output enable delay (all outputs) 1 10 ns
t
PHZ,tPLZ
Output disable delay (all outputs) 1 10 ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
mA
mA
Input Capacitance
1
I
DD2.5OP
µ
APowerdown Current
Operating Supply
Curre nt
Input Low Current
µ
A
mA
mA
I
DD3.3OP
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
9
ICS9250-26
Electrical Characteristics - CPU
TA = 0 - 70C; V
DDL
= 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP2B
1
VO = VDD*(0.5) 13.5 16 45
Ω
Output Impedance R
DSN2B
1
VO = VDD*(0.5) 13.5 21 45
Ω
Output High Voltage V
OH2B
IOH = -1 mA 2 V
Output Low Voltage V
OL2B
IOL = 1 mA 0.4 V
V
OH @ MIN
= 1.0 V -27 -68
V
OH @ MAX
= 2.375 V -9 -27
V
OL @ MIN
= 1.2 V 27 54
V
OL @ MAX
= 0.3 V 11 30
Rise Time
1
t
r2B
VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns
Fall Time
1
t
f2B
VOH = 2.0 V, VOL = 0.4 V 0.4 1.1 1.6 ns
V
T
= 1.25 V, 66, 100 MHz 45 49 55
V
T
= 1.25 V, 133 MHz 40 48 55
Skew window
1
t
sk2B
VT = 1.25 V 65 175 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
VT = 1.25 V
90 250 ps
1
Guaranteed by design, not 100% tested in production.
%
d
t2B
Duty Cycle
1
mA
mA
Output High Curre nt
Output Low Current
I
OH2B
I
OL2B
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1B
1
VO = VDD*(0.5) 12 14 55
Ω
Output Impedance R
DSN1B
1
VO = VDD*(0.5) 12 14.5 55
Ω
Output High Volt age V
OH1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL1
IOL = 1 mA 0.55 V
V
OH @ MIN
= 1.0 V -33 -108
V
OH @ MAX
= 3.135 V -9 -33
V
OL @ MIN
= 1.95 V 30 95
V
OL @ MAX
= 0.4 V 29 38
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 0.4 1.2 1.6 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 0.4 1.2 1.6 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 49 55 %
Skew window
1
t
sk1
VT = 1.5 V 65 175 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc1
VT = 1.5 V
120 500 ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
Output Low Current
mA
mA
I
OH1
I
OL1
10
ICS9250-26
Electric al Characteristics - IOAPIC
TA = 0 - 70C; V
DDL
= 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PA RAM ETER SYMBOL CONDITIONS MIN TYP M AX UNITS
Output Impedance R
DSP4 B
1
VO = VDD*(0.5) 9 16 30
Ω
Output Impedance R
DSN4 B
1
VO = VDD*(0.5) 9 20 30
Ω
Output High V oltage V
OH4B
IOH = -1 mA 2 V
Output Low Volta ge V
OL4B
IOL = 1 mA 0.4 V
V
OH @ MIN
= 1.0 V -27 -68
V
OH @ MAX
= 2.375 V -9 -27
V
OL @ MI N
= 1.2 V 27 54
V
OL @ MAX
= 0.3 V 11 30
Rise Time
1
t
r4B
VOL = 0.4 V, VOH = 2.0 V 0.4 1.1 1.6 ns
Fall Time
1
t
f4 B
VOH = 2.0 V, VOL = 0.4 V 0.4 1.1 1.6 ns
Duty Cycle
1
d
t4B
VT = 1.25 V 45 49 55 %
Skew window
1
t
sk4B
VT = 1.25 V 25 250 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc4BVT
= 1.25 V
150 500 ps
1
Guaranteed by design, not 100% tested in production.
Output High Current I
OH4B
mA
Output Low Current I
OL4B
mA
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP3B
1
VO = VDD*(0.5) 10 12 24
Ω
Output Impedance R
DSN3B
1
VO = VDD*(0.5) 10 15 24
Ω
V
OH @ MIN
= 2.0 V -54 -92
V
OH @ MAX
= 3.135 V -16 -46
V
OL @ MIN
= 1.0 V 54 68
V
OL @ MAX
= 0.4 V 29 53
Rise Time
1
t
r3
VOL = 0.4 V, VOH = 2.4 V 0.4 1 1.6 ns
Fall Time
1
t
f3
VOH = 2.4 V, VOL = 0.4 V 0.4 1.5 1.6 ns
Duty Cycle
1
d
t3
VT = 1.5 V 45 52 55 %
Skew window
1
t
sk3
VT = 1.5 V 85 250 ps
V
T
= 1.5 V, 66, 100 MHz 120 250
V
T
= 1.5 V, 133 MHz
150 300
1
Guaranteed by design, not 100% tested in production.
Jitter, Cycle-to-cycle
1
t
jcyc-cyc3
ps
mA
mA
Output High Current
Output Low Current
I
OH3
I
OL3
11
ICS9250-26
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP1B
1
VO = VDD*(0.5) 12 15 55
Ω
Output Impedance R
DSN1B
1
VO = VDD*(0.5) 12 15 55
Ω
Output High Volt age V
OH1
IOH = -1 mA 2.4 V
Output Low Voltage V
OL1
IOL = 1 mA 0.55 V
V
OH @ MIN
= 1.0 V -33 -106
V
OH @ MAX
= 3.135 V -14 -33
V
OL @ MIN
= 1.95 V 30 94
V
OL @ MAX
= 0.4 V 29 38
Rise Time
1
t
r1
VOL = 0.4 V, VOH = 2.4 V 0.4 1.3 2 ns
Fall Time
1
t
f1
VOH = 2.4 V, VOL = 0.4 V 0.4 1.4 2 ns
Duty Cycle
1
d
t1
VT = 1.5 V 45 51 55 %
Skew window
1
t
sk1
VT = 1.5 V 250 500 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc1
VT = 1.5 V
150 500 ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH1
mA
Output Low Current
I
OL1
mA
Electric al Characteristics - REF, 48MHz_0 (Pin 25)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PA RAM ETER SYMBOL CONDITIONS MIN TYP M AX UNITS
Output Impedance R
DSP5 B
1
VO = VDD*(0.5) 20 29 60
Ω
Output Impedance R
DSN5 B
1
VO = VDD*(0.5) 20 27 60
Ω
Output High V oltage V
OH15
IOH = -1 mA 2.4 V
Output Low Volta ge V
OL5
IOL = 1 mA 0.55 V
V
OH @ MIN
= 1.0 V -29 -54
V
OH @ MAX
= 3.135 V -11 -23
V
OL @ MI N
= 1.95 V 29 54
V
OL @ MAX
= 0.4 V 16 27
Rise Time
1
t
r5
VOL = 0.4 V, VOH = 2.4 V 0.4 1.1 4 ns
Fall Time
1
t
f5
VOH = 2.4 V, VOL = 0.4 V 0.4 1.6 4 ns
Duty Cycle
1
d
t5
VT = 1.5 V 45 53 55 %
Jitter, Cycle-to-cycle
1
t
jcyc-cyc5
VT = 1.5 V, Fixed clocks 130 500 ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc5
VT = 1.5 V, Ref clocks
650 1000 ps
1
Guaranteed by design, not 100% tested in production.
Output High Current I
OH5
mA
Output Low Current I
OL5
mA
12
ICS9250-26
Electrical Characteristics - 48MHz_1 (Pin 26)
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Impedance R
DSP3B
1
VO = VDD*(0.5) 10 15 24
Ω
Output Impedance R
DSN3B
1
VO = VDD*(0.5) 10 15 24
Ω
Output High Volt age V
OH3
IOH = -1 mA 2.4 V
Output Low Voltage V
OL3
IOL = 1 mA 0.55 V
V
OH @ MIN
= 2.0 V -54 -82
V
OH @ MAX
= 3.135 V -20 -46
V
OL @ MIN
= 1.0 V 54 95
V
OL @ MAX
= 0.4 V 28 53
Rise Time
1
t
r3
VOL = 0.4 V, VOH = 2.4 V 0.4 1.1 1.6 ns
Fall Time
1
t
f3
VOH = 2.4 V, VOL = 0.4 V 0.4 1.3 1.6 ns
Duty Cycle
1
d
t3
VT = 1.5 V 45 53 55 %
Jitter, Cycle-to-cycle
1
t
jcyc-cyc3B
VT = 1.5 V
130 250 ps
1
Guaranteed by design, not 100% tested in production.
Output High Current
I
OH3
mA
Output Low Current
I
OL3
mA
Group Skews (CPU = 66 MHz )
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveform diagram for definition of transition edges.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CPU to SDRAM Skew
1
T
sk1 CPU-SDRAM
-3 -2.6 -2 ns
Skew Window
1
T
w1 CPU-SDRAM
0 150 500 ps
CPU to 3V66 Skew
1
T
sk1 CPU-3V66
77.28ns
Skew Window
1
T
w1 CPU-3V66
0 130 500 ps
SDRAM to 3V66 Skew
1
T
sk1 SDRAM-3V66
-500 100 500 ps
Skew Window
1
T
w1 SDRAM-3V66
0 155 500 ps
3V66 to PCI Skew
1
T
sk1 3V66-PCI
1.5 2.4 3.5 ns
Skew Window
1
T
w1 3V66-PCI
0 275 500 ps
IOAPIC to PCI Skew
1
T
sk1 IOAPIC-PCI
-1 -0.4 1 ns
Skew Window
1
T
w1 IOAPIC-PCI
00.251 ns
1
Guaranteed by design, not 100% tested in production.
CPU @ 1.25 V, SDRAM @ 1.5 V
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
13
ICS9250-26
Group Skews (CPU = 100 MHz )
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveform diagram for definition of transition edges.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CPU to SDRAM Skew
1
T
sk2 CPU-SDRAM
4.5 4.9 5.5 ns
Skew Window
1
T
w2 CPU-SDRAM
0 140 500 ps
CPU to 3V66 Skew
1
T
sk2 CPU-3V66
4.5 4.8 5.5 ns
Skew Window
1
T
w2 CPU-3V66
0 150 500 ps
SDRAM to 3V66 Skew
1
T
sk2 SDRAM-3V66
-500 100 500 ps
Skew Window
1
T
w2 SDRAM-3V66
0 155 500 ps
3V66 to PCI Skew
1
T
sk2 3V66-PCI
1.5 2.4 3.5 ns
Skew Window
1
T
w2 3V66-PCI
0 275 500 ps
IOAPIC to PCI Skew
1
T
sk2 IOAPIC-PCI
-1 -0.4 1 ns
Skew Window
1
T
w2 IOAPIC-PCI
00.251 ns
1
Guaranteed by design, not 100% tested in production.
1
Guaranteed by design, not 100% tested in production.
CPU @ 1.25 V, SDRAM @ 1.5 V
CPU @ 1.25 V, 3V66 @ 1.5 V
SDRAM, 3V66 @ 1.5 V
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
Group Skews (CPU = 133 MHz )
TA = 0 - 70º C; VDD = 3.3 V +/-5%, V
DDL
= 2.5 V +/-5%
CPU & IOAPIC load (lumped) = 20 pF; PCI, SDRAM, 3V66 load (lumped) = 30 pF
Refer to Group Offset Waveform diagram for definition of transition edges.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
CPU to SDRAM Skew
1
T
sk3 CPU-SDRAM
-500 70 500 ps
Skew Window
1
T
w3 CPU-SDRAM
0 125 500 ps
CPU to 3V66 Skew
1
T
sk3 CPU-3V66
-500 -145 500 ps
Skew Window
1
T
w3 CPU-3V66
0 220 500 ps
SDRAM to 3V66 Skew
1
T
sk3 SDRAM-3V66
-500 100 500 ps
Skew Window
1
T
w3 SDRAM-3V66
0 155 500 ps
3V66 to PCI Skew
1
T
sk3 3V66-PCI
1.5 2.4 3.5 ns
Skew Window
1
T
w3 3V66-PCI
0 275 500 ps
IOAPIC to PCI Skew
1
T
sk3 IOAPIC-PCI
-1 -0.4 1 ns
Skew Window
1
T
w3 IOAPIC-PCI
00.251 ns
1
Guaranteed by design, not 100% tested in production.
3V66, PCI @ 1.5 V
IOAPIC @ 1.25 V, PCI @ 1.5 V
SDRAM, 3V66 @ 1.5 V
CPU @ 1.25 V, SDRAM @ 1.5 V
CPU @ 1.25 V, 3V66 @ 1.5 V
14
ICS9250-26
Group Offset Waveforms
Power Down Waveform
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
15
ICS9250-26
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Ordering Information
ICS9250yF-26-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
MIN MAX MIN MAX
A 2.413 2.794 .095 .110
A1 0.203 0.406 .008 .016
b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420
E1 7.391 7.595 .291 .299
e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N
α
0° 8° 0° 8°
VARIATIONS
MIN MAX MIN MAX
56 18.288
18.542
.720 .730
JEDEC MO-118
DOC# 10-0034
6/1/00
REV B
N
D mm.
D (inch)
SEE VARIATIONS
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
SEE VARIATIONS
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