ICST AV9250F-26-T, ICS9250F-26-T Datasheet
Integrated
Circuit
Systems, Inc.
ICS9250-26
Third party brands and names are the property of their respective owners.
Block Diagram
9250-26 Rev B 01/19/01
Recommended Application:
810/810E type chipset. Provides three CPU speeds
(66.6, 100, 133MHz) with SDRAM = 133.3MHz.
Output Features:
• 3 CPU (2.5V) 66.6/133.3MHz (up to 150MHz
achievable through I
2
C)
• 9 SDRAM (3.3V) @ 133.3MHz (up to 150MHz
achievable through I
2
C)
• 8 PCI (3.3 V) @33.3MHz
• 2 IOAPIC (2.5V) @ 33.3 MHz
• 2 Hublink clocks (3.3 V) @ 66.6 MHz
• 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)
• 1 REF (3.3V) @ 14.318 MHz
Features:
• Supports spread spectrum modulation ,
down spread 0 to -0.5% and ± 0.25% center spread.
•I
2
C support for power management
• Efficient power management scheme through PD#
• Uses external 14.138 MHz crystal
• Alternate frequency selections available through I
2
C
control.
Functionality
Pin Configuration
56-Pin 300mil SSOP
* This input has a 120KΩ pull-down to GND.
*FS2//REF0
VDD0
X1
X2
GND0
GND1
3V66-0
3V66-1
VDD1
VDD2
PCICLK0
PCICLK1
PCICLK2
GND2
PCICLK3
PCICLK4
GND2
PCICLK5
PCICLK6
PCICLK7
VDD2
VDD3
GND3
GND4
48MHz_0
48MHz_1
VDD4
FS0
GNDL1
IOAPIC0
IOAPIC1
VDDL1
CPUCLK0
VDDL0
CPUCLK1
CPUCLK2
GNDL0
GND5
SDRAM0
SDRAM1
VDD5
SDRAM2
SDRAM3
GND5
SDRAM4
SDRAM5
VDD5
SDRAM6
SDRAM7
GND5
SDRAM_F
VDD5
PD#
SCLK
S DATA
FS1
ICS9250-26
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Frequency Generator & Integrated Buffers for Celeron & PII/III™
2SF1SF0SFnoitcnuF
X00 etatsirT
X0 1tseT
010
zHM66=UPCevitcA
zHM001=MARDS
011
zHM001=UPCevitcA
zHM001=MARDS
111
zHM331=UPCevitcA
zHM001=MARDS
110
)noitidnoClaicepS(
zHM331=UPCevitcA
zHM331=MARDS
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9250-26
The ICS9250-26 is a single chip clock solution for 810/810E type chipset. It provides all necessary clock signals for
such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This
simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-26 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
General Description
Pin Configuration
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1
2SFTUO
tuptuolla,ycneuqerfUPCsenimreteD.niptceleSnoitcnuF
05htiw(ytilanoitcnuf Ω)
0FERTUO.tuptuokcolcecnereferzHM813.41,V3.3
31XTUO
kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
42XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp33(pac
,32,42,53,14,74
5,6,41,71
)0:5(DNGRWPylppusV3.3rofsnipdnuorG
7,8]0:1[66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3
,22,72,33,83,44
2,9,01,01,12
)0:5(DDVRWPylppusrewopV3.3
,61,81,91,02
11,21,31,51
)0:7(KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3
52,62)0:1(zHM84TUOBSUrofstuptuokcolczHM84dexiFV3.3
82,92)0:1(SFTUO
tuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF
.3egapnoelbatytilanoitcnuFotreferesaelP.ytilanoitcnuf
03ATADSNIIroftupniataD
2
.tupnilairesC
13KLCSNIIfotupnikcolC
2
tupniC
23#DPNI
ecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA
ehtdnadelbasideraskcolclanretniehT.etatsrewopwolaotni
nwodrewopehtfoycnetalehT.deppotseralatsyrcehtdnaOCV
.sm3nahtretaergebtonlliw
,24,04,93,73,63
64,54,34
)0:7(MARDSTUO
denrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3
Ihguorhtffo
2
C
43F_MARDSTUOIybdetceffatonMARDSzHM001gninnureerfV3.3
2
C
84,65)0:1(LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG
94,05,25)0:2(KLCUPCTUO
zHM331zHM001rozHM66.tuptuokcolcsubtsoHV5.2
snipSFnognidneped
35,15)0:1(LDDVRWPCIPAOI&UPCrofylppyusrewopV5.2
55,45)0:1(CIPAOITUO.zHM3.33tagninnurstuptuokcolcV5.2
3
ICS9250-26
Maximum Allowed Current
E018
noitidnoC
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V526.2=2qddV
DNGro3qddV=stupnicitatsllA
noitpmusnocylppusV5.2xaM
,sdaolpacetercsidxaM
V564.3=2qddV
DNGro3qddV=stupnicitatsllA
edoMnwodrewoP
0=#NWDRWP(
Am01Am01
zHM66evitcAlluF
01=0,1LES
Am07Am082
zHM001evitcAlluF
11=0,1LES
Am001Am082
Clock Enable Configuration
#DPKLCUPCMARDSCIPAOIzHM66KLCICP
,FER
zHM84
csOsOCV
0WOLWOLWOLWOLWOLWOLFFOFFO
1NONONONONONONONO
Power Groups*
VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66
VDD2, GND2 = PCICLK
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz
VDD5, GND5 = SDRAM_F, SDRAM
VDDL0, GNDL0 = CPUCLK
VDDL1, GNDL1 = IOAPIC
* To ensure the processor will power up to the desired frequency, the 3.3V supply to the ICS9250-26 needs to reach a stable
condition before the 2.5V supply does. In most systems, the power up ramp of the 2.5V is slower than the 3.3V ramp. For those
instances, no special requirements are necessary.
4
ICS9250-26
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5. To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2
(H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3
(H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
A
CK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
A
CK
Dummy Command Code
A
CK
Dummy Byte Count
A
CK
Byte 0
A
CK
Byte 1
ACK
Byte 2
A
CK
Byte 3
A
CK
Byte 4
A
CK
Byte 5
A
CK
Stop Bit
How to Write:
5
ICS9250-26
tiBnoitpitcseDDWP
7tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
6tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
5tiB )lamronetarepootkcolc0ebotsdeeN(TIBDEVRESERSCI0
tiB
)0,3(
)0,3(tiB
KLCUPC
zHM
MARDS
zHM
66V3
zHM
KLCICP
zHM
XXXX
1etoN
2SF
)WH(
0SF
)WH(
1LES
)3tiB(
0LES
)0tiB(
0000 76.6600.00106.6603.33
0001 00.0700.50100.0700.53
0010 76.2700.90176.2733.63
0011 76.4700.21166.4733.73
0100 00.00100.00106.6603.33
0101 00.50100.50100.0700.53
0110 00.90100.90176.2733.63
0111 10.21100.21166.4733.73
1000 43.33143.33166.8833.44
1001 00.04100.50100.0700.53
1010 00.02100.0900.0600.03
1011 00.42100.42166.2833.14
1100 43.33100.00106.6603.33
1101 00.05100.05100.5705.73
1110 00.04100.04100.0700.53
1111 99.23199.23106.6603.33
4tiB
%5.-ot0murtcepSdaerpSdaerpSnwoD=0
%52.±murtcepSdaerpSdaerpSretneC=1
0
2tiB)noitarepokcolclamronrof1ebotsdeeN(desutoN 1
1tiB)noitarepokcolclamronrof1ebotsdeeN(desutoN 1
Byte 5: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Note1: Default at power-up will be for Bit 3 and Bit 0 to be 00, with external hardware selection of FS0, FS2
defining specific frequency.
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