ICST AV9250F-14-T, ICS9250F-14-T Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9250-14

Block Diagram

Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Timing Generator for Pentium II Systems

9250-14 Rev A 2/5/00

Pin Configuration

 Generates the following system clocks:

- 2 - CPUs @ 2.5V, up to 150MHz.

- 1 - IOAPIC @ 2.5V, PCI or PCI/2MHz.

- 13 SDRAMs (3.3V) @ 150MHz.

- 2 - 3V66 @ 3.3V, 2x PCIMHz.

- 8 - PCIs @ 3.3V.

- 1 - 48MHz, @ 3.3V fixed.

- 2 - REF @ 3.3V, 14.318Hz.

- 1 - 24MHz, @ 3.3V fixed.

 Supports spread spectrum modulation ,

± .25% center spread.

I

2

C support for power management
 Efficient power management scheme through PD#
 Uses external 14.138 MHz crystal

56-Pin 300 mil SSOP

The ICS9250-14 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9250-14
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Power Groups

GNDREF, VDDREF = REF, Crystal
GND3V66, VDD3V66 = 3V66
GNDPCI, VDDPCI = PCICLKs
GNDCOR, VDDCOR = PLLCORE
GND48, VDD48 = 48
GNDSDR, VDDSDR = SDRAM
GNDLCPU, VDDLCPU = CPUCLK
GNDLPCI, VDDLAPIC = IOAPIC

1. These pins will have 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.

Skew Specifications

 CPU  CPU: <175ps
 SDRAM - SDRAM: < 250ps
 3V66  3V66: <250ps
 PCI  PCI: <500ps
 CPU-SDRAM<500ps
 CPU(early)-PCI: MIN=1.0ns,TYP=2.0,MAX=4.0
 CPU-3V66<500ps
 3V66(early)-PCI: MIN=1.5ns,TYP=2.0,MAX=4.0
 IOAPIC-PCI<500ps

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

Preliminary Product Preview

2

ICS9250-14

Preliminary Product Preview

Pin Descriptions

NIP

REBMUN

EMANNIPEPYTNOITPIRCSED

11FERTUO.tuptuokcolcecnereferzHM813.41,V3.3

,52,81,01,9,2

54,73,23

DDVRWPylppusrewopV3.3

31XNI

kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

42XTUO

daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC

)Fp33(pac

,12,41,6,5

,63,92,82

94,14

DNGRWPylppusV3.3rofsnipdnuorG

8,7)1;0(66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3

11

0KLCICP

1

TUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

0SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

21

1KLCICP

1

NISKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

1SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

,61,51,31

02,91,71

)7:2(KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

22#DPNI

otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA

dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola

ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht

.sm3nahtretaerg

32KLCSNIIfotupnikcolC

2

tupniC

42ATADSNIIroftupniataD

2

.tupnilairesC

43

zHM84TUOBSUroftuptuokcolczHM84dexiFV3.3

3SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

53

2SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

zHM42TUOtuptuozHM42dexifV3.3

83F_MARDSTUOIybdetceffatonMARDSzHM001gninnureerfV3.3

2

C

,13,03,72,62
,34,24,04,93

84,74,44

)0:11(MARDSTUO

ffodenrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3

Ihguorht

2

C

05LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG

25,15)1:0(KLCUPCTUO

SFnognidnepedzHM001rozHM66.tuptuokcolcsubtsoHV5.2

.3egaprefeRsnip)1:0(

55,35LDDVRWPCIPAOI,UPCrofylppyusrewopV5.2

45CIPAOITUO.zHM76.61tagninnurstuptuokcolcV5.2
65

4SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

0FER

1

TUO.tuptuokcolcecnereferzHM813.41,V3.3

Note:

1. These pins will have 2X drive strength.

3

ICS9250-14

Preliminary Product Preview

Frequency Selection

Clock Enable Configuration

Note:
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.

4SF3SF2SF1SF0SF

UPC

zHM

MARDS

zHM

zHM66V3

ICP

zHM

zHMCIPAOI

00000 18.7617.10118.7609.3359.61
00001 00.0700.50100.0700.5305.71
00010 10.2710.80110.2700.6300.81
00011 76.6600.00176.6633.3376.61
00100 10.3715.90110.3705.6352.81
00101 00.5705.21100.5705.7357.81
00110 00.7705.51100.7705.8352.91
00111 10.8710.71110.8700.9305.91
01000 00.0800.02100.0800.0400.02
01001 00.3815.42100.3805.1457.02
01010 94.4847.62194.4852.2421.12
01011 00.00100.05100.00100.0500.52
01100 80.6821.92180.6840.3425.12
01101 00.8800.23100.8800.4400.22
01110 00.0900.53100.0900.5405.22
01111 00.5905.24100.5905.7457.32

10000 09.9409.9462.3336.6123.8
1000 1 00.00100.00166.6633.3376.61
100 10 58.4758.4709.9459.4274.21
100 11 85.6685.6693.4491.2201.11
10 100 48.2848.2832.5516.7218.31
10 10 1 18.9818.9888.9549.9279.41
10 110 08.4908.4902.3606.1308.51
10111 05.00105.00100.7605.3357.61
11000 87.40187.40168.9639.4364.71
11001 77.11177.11125.4762.7336.81
11010 77.41177.41115.6762.8331.91
11011 00.00100.00166.6633.3376.61
11100 57.32157.32105.2852.1426.02
11101 47.23147.23194.8852.4421.22
11110 57.93157.93161.3985.6492.32
11111 96.94196.94197.9909.9459.42

#DPKLCUPCMARDSCIPAOIzHM66KLCICP

,FER

zHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLFFOFFO

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4

ICS9250-14

Preliminary Product Preview

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz