ICST AV9250F-12-T, ICS9250F-12-T Datasheet

General Description Features

ICS9250-12

Integrated
Circuit
Systems, Inc.

Block Diagram

Frequency Timing Generator for PENTIUM II/III Systems

9250-12 Rev B 2/23/00

Pin Configuration

56-pin SSOP

 Generates the following system clocks:

- 4 CPU clocks ( 2.5V, 100/133MHz)

- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)

- 2 CPU/2 clocks (2.5V, 50/66MHz)

- 3 IOAPIC clocks (2.5V, 16.67MHz)

- 4 Fixed frequency 66MHz clocks(3.3V, 66MHz)

- 2 REF clocks(3.3V, 14.318MHz)

- 1 USB clock (3.3V, 48MHz)

 Efficient power management through PD#, CPU_STOP#

and PCI_STOP#.

 0.5% typical down spread modulation on CPU, PCI,

IOAPIC, 3V66 and CPU/2 output clocks.

 Uses external 14.318MHz crystal.

The ICS9250-12 is a main clock synthesizer chip for
Pentium II based systems using Rambus Interface DRAMs.
This chip provides all the clocks required for such a system
when used with a Direct Rambus Clock Generator (DRCG)
chip such as the ICS9212-01, 02, 03 and a PCI buffer 9112-17.

Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI
by 8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9250-12 employs a proprietary closed loop design,
which tightly controls the percentage of spreading over
process and temperature variations.

The CPU/2 clocks are inputs to the DRCG.

Key Specification:

 CPU Output Jitter: 150ps
 IOAPIC Output Jitter: 250ps
 CPU/2, 3V66, PCI Output Jitter: 250ps
 CPU (0:3) CPU/2 Output Skew: <175ps
 PCI_F, PCI 1:7 Output Skew: <500ps
 3V66 (0:3) Output Skew <250ps
 IOAPIC (0:2) Output Skew <250ps
 CPU to 3V66 (0:3) Output Offset: 0.0 - 1.5ns (CPU leads)
 CPU to PCI Output Offset: 1.5 - 4.0ns (CPU leads)
 CPU to APIC Output Offset 1.5 - 4.0ns (CPU leads)

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9250-12

Pin Descriptions

Pin number Pin name Type Description

1 GN DREF PWR Gnd pin for R EF clocks
2, 3 REF(0:1) OUT 14.318MH z reference clock outputs at 3.3V
4 VDDREF PWR Power pin for REF clocks

5 X1 IN XTAL_IN 14.318MHz crystal input
6 X2 OUT XTAL _OUT Cr ystal output
7, 13, 19 GNDPCI PWR Gnd pin for PCICLKs

8 PCICLK_F OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected
by the PCI_STOP# input.

9, 11, 12, 14, 15,
17, 18

PCICLK[1:7] OUT PC I clock outputs at 3.3V. Synchronous to CPU clocks.

10, 16 VDDPCI PWR 3.3Volts power pin for PCICLKs
20, 24 GND66 P WR Gnd pin for 3V66 outputs

21, 22, 25, 26 3V66[0:3] OUT

66MHz outputs at 3.3V. These outputs are stopped when CPU_S TOP# is
driven active..

23, 27 VDD66 PWR power pin for the 3V66 clocks.
28 SEL 133/100# IN

This selects the frequency fo r the CPU and CPU/2 outputs. High =

133MHz, Low=100MHz
29 G ND48 PWR G round pin for the 48M Hz output
30 48M Hz OUT Fixed 48MHz clock output. 3.3V
31 V DD48 PWR P o wer pin for the 48MHz output.
32, 33 SEL[0:1] IN F unction select pins. See truth table for details.

34 S P READ # IN

Enables spread spectrum when active(Low). modulates all the CP U, PCI,

IOAP IC, 3V66 and CPU/2 clocks. Does not affect the REF and 48MHz

clocks. 0.5% down spread modulation.

35 PD# IN

This asyn chronous input powers down the chip when drive active(Lo w).

The internal PLLs are disabled and all the output clocks are held at a Low

state.
36 CPU_STOP# IN

This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at

l

ogic "0" when driven active( Low). Does not affect the CPU/2 clocks.

37 PCI_STOP# IN

This asynchronous input halts the PCICLK[1:7] at logic"0" when driven

active(Low). PCICLK_F is not affected by this input.
38 G NDCOR PWR Ground pin for the PLL core

39 V DDCOR PWR P ower pin for the PLL core. 3.3V
43, 47 VDDLCPU PWR Pow er pin for the CP UCLKs. 2.5V
40, 44 GNDLCPU PWR Ground pin for the CPU C LKs

41, 42, 45, 46 CPUCLK[0:3] OUT

Host bus clock output at 2.5V. 133MHz or 100MHz depending on the state

of the SEL 133/100MHz.
48 GNDLCPU/2 PWR Ground pin for the CPU/2 clocks.

49, 50 CPU/2[0:1] OUT

2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on

the state of the SEL 133/100# input pin.
51 V DDLCPU/2 PWR Power pin for the CPU /2 clocks. 2.5V
52 G NDLIOAPIC PWR Ground pin for the IOAPIC outputs.

53, 54, 55 IOAPIC[0:2] OUT

IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at

16.67MHz.

56 V DDLIOAP IC PWR Pow er pin for the IO APIC outputs. 2.5V.

3

ICS9250-12

Frequency Select:

Note:

1. TCLK is a test clock driven on the x1 input during test mode.

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.FER

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ICS9250-12 Power Management Features:

Note:

1. LOW means outputs held static LOW as per latency requirement next page.

2. On means active.

3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.

4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.

5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions
except PD# = LOW

Power Groups:

VDDREF, GNDREF = REF, X1, X2
GNDPCI, VDDPCI = PCICLK
VDD66, GND66 = 3V66
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLIOAPIC, GNDIOAPIC = IOAPIC

LES

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101 A/NA/NA/NA/NA/NA/NA/NdevreseR
110 331666633Z-iH813.4176.61
111 33166663384813.4176.61

4

ICS9250-12

Power Management Requirements:

Note:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.

2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.

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CPU_STOP# Timing Diagram

CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power
operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI
clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run
while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse. ONLY one rising edge of PCICLK_F is allowed after the clock control logic
switched for both the CPU and 3V66 outputs to become enabled/disabled.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. The internal label means inside the chip and is a reference only. This
in fact may not be the way that the control is designed.

3. CPU_STOP# signal is an input singal that must be made synchronous
to free running PCICLK_F

4. 3V66 clocks also stop/start before

5. PD# and PCI_STOP# are shown in a high state.

6. Diagrams shown with respect to 133MHz. Similar operation when CPU
is 100MHz