ICST AV9250F-11-T, ICS9250F-11-T Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9250-11

Third party brands and names are the property of their respective owners.

Block Diagram

Frequency Timing Generator for PENTIUM II/III Systems

9250-11 Rev C 3/20/00

Pin Configuration

56-pin SSOP



Generates the following system clocks:

- 6 - CPU Clocks 100/133MHz (2.5V).

- 2 - CPU/2 output for synchronous memory

reference (2.5V).

- 4 - fixed frequency Clocks @ 66.6MHz (3.3V).

- 2 - fixed frequency Clocks @ 33.3MHz (3.3V).

- 6 - IOAPIC Clocks @ ¼ of CPUCLK or 16.667MHz,

synchronous to CPU Clock (2.5V)

- 1 - 48MHz Clock (3.3V)

- 2 - REF Clocks @ 14.31818MHz

 0.5% typical down spread modulation on CPU, PCI,

IOAPIC, 3V66 and CPU/2 output clocks.

 Uses external 14.318MHz crystal.

The ICS9250-11 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator (DRCG) chip such as
the ICS9212-01, 02, 03 and a PCI buffer 9112-17.

Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9250-11 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process and
temperature variations.

The CPU/2 clocks are inputs to the DRCG.

SEL 133/100#

SEL(0:1)

SPREAD#

X1
X2

OSC

PLL

Spread

Spectrum

PLL2

CPU/2 (0:1)

REF (0:1)

2

6

4

2

2

CPUCLK (0:5)

3V66 (0:3)

48MHz

/ 2

/ 3 / 2

3V33 (0:1)

C
o
n

t
r

o

l

/ 2

/ 2

/ 4

/ 3

/ 2

IOAPIC(0:5)

6

Power Groups:

VDDREF, GNDREF = REF, X1, X2
VDD66, GND66 = 3V66
VDD33, GND33 = 3V33
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU, GNDLCPU = CPUCLK
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLAPIC, GNDAPIC = IOAPIC

ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.

2

ICS9250-11

Pin Descriptions

Pin number Pin name Type Description

1, 52, 53 GNDLAPIC PWR Ground pin for the IOA PIC outputs.

2, 3, 50, 51, 54, 55 IOAP IC ( 0: 5) OUT

2.5V clock outputs run ning di vi de synchronous w it h t h e C PU
(Host bus) clock f requency. The default API C is r unni ng at ¼ of
CP UCLK frequenc y .

When FREQ _APIC is strapped low, the APIC is running at fixed

16.67 M Hz.
If CPU = 133 MHz, APIC = CPU/8
If CPU = 100 MHz, APIC = CPU/6

4, 49, 56 VDDLAPIC PWR Power pin for the IOAPI C out put s. 2.5V.

5, 11 V DDREF PWR Power pin for REF clocks

6 X1 IN X TA L_IN 14.318MHz cryst a l i nput
7 X2 OUT XTAL_O UT Crystal out pu t

REF0 OUT

3.3V 14.318 MHz clock output. APIC cloc k strapping option for
fi xe d 16.67 MHz APIC c l ock outputs.

FREQ_APIC# OUT

If FREQ_APIC# = 0, APIC Cloc k = 16.67 MHz
If FREQ_AP IC# = O pen, AP IC Clock = CPU/4

REF1 OUT 3.3V 1 4.318MHz c lock output.

TEST# OUT

TE ST# is sa mpled lo w (external wi th 10 k pu l ldown). All cl ock
outputs are Tri -St a te .

12, 19 VDD66 PWR pow e r pin for the 3V66 clocks.

13, 14, 17, 18 3V 66[0:3] OUT

66MH z output s a t 3.3V . These outputs ar e s t oppe d when
CPU_ST OP# is driven ac tive ..

8, 15, 16, 23, 2 4 G ND PWR Ground pin for 3V outputs.

21, 22 3V 33MHz OUT 3.3V F i xe d 33MHz clock outpu t .

25 VDDCOR PWR 3.3V power for PLL core.
26 GND48 PWR Ground pin for the 48MHz output
27 48MH z OUT Fixed 48MHz clock out p ut. 3.3V
28 VDD48 PWR Power pin for the 48MHz output .

29 S EL 133/100# IN

This sel ects t he freque nc y for the CPU and CPU/ 2 out p ut s. High =
133MH z, Low=100MHz

30, 31 SEL[0:1] I N Function select pi n s. See t ruth table for details.

32 SPREAD# IN

Enables spr e ad s pectrum when active(Low). modulates all the CP U,
PC I, IOAP IC, 3V 66 a n d C PU/2 clocks. Does not a ffect t he REF and
48MH z c l ocks. 0.5% down spread mo dul ation.

33 VDDLCPU/2 PWR Power pin for the CPU/2 clocks. 2.5V

34, 35 CPU/2[ 0: 1] OUT

2.5V clock outputs at 1/2 C PU frequency. 66MHz or50MHz
dependi ng on t he stat e of the SEL 133/100# input pi n.

36 GNDLCPU/2 PWR Ground pin for the CPU/2 clocks .

37, 4 4, 45 GNDLCP U PWR Ground pi n for the C PUCLKs

38, 39, 42, 43, 46,

47

CPUCLK[0:5] OUT

Ho st bus clock output at 2.5 V. 133MH z or 100MHz depending on
the st a te of the S E L 133/100MHz.

40, 41, 48 VD DLCP U PWR Pow er pin for the CP UCLKs. 2.5V

9

10

3

ICS9250-11

Frequency Select:

Power Management Features:

LES

#001/331

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011 00100.056.663.3384813.4176.61/KLCUPC¼
100 2/KLCT4/KLCT4/KLCT8/KLCT2/KLCTKLCT61/KLCT
101 A/NA/NA/NA/NANA/NA/N
110 3.3316.666.663.33FFO813.4176.61/KLCUPC¼
111 3.3316.666.663.3384813.4176.61/KLCUPC¼

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