ICST AV9250F-10-T, ICS9250F-10-T Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9250-10

PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

Preliminary Product Preview

Block Diagram

Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Timing Generator for Pentium II Systems

9250-10 Rev J 6/15/99

Pin Configuration

 Generates the following system clocks:

- 3 CPU (2.5V) 66.6/100 MHz (up to 133MHz through

I2C selection)

- 9 SDRAM (3.3V) up to 133MHz

- 8 PCI (3.3 V) @33.3MHz

- 2 IOAPIC (2.5V) @16.67 or 33.3MHz

- 2 Hublink clocks (3.3 V) @ 66.6 MHz

- 2 USB (3.3V) @ 48 MHz ( Non spread spectrum)

- 1 REF (3.3V) @ 14.318 MHz

 Supports spread spectrum modulation ,

down spread 0 to -0.5%
I2C support for power management
 Efficient power management scheme through PD#
 Uses external 14.138 MHz crystal

56-Pin 300 mil SSOP

The ICS9250-10 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9250-10
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Power Groups

VDD0, GND0 = REF & Crystal
VDD1, GND1 = 3V66 [1:0]
VDD2, GND2 = PCICLK[7:0]
VDD3, GND3 = PLL core
VDD4, GND4 = 48MHz [1:0]
VDD5, GND5 = SDRAM_F, SDRAM [7:0]
VDDL0, GNDL0 = CPUCLK [2:0]
VDDL1, GNDL1 = IOAPIC [1:0]

*60K ohm pull-up to VDD on indicated inputs.

2

ICS9250-10

Preliminary Product Preview

Pin Descriptions

REBMUNNIPEMANNIPEPYTNOITPIRCSED

1

CIPA_QERFNI

.ycneuqerfCIPAOIehtsenimretedsiht.nOrewoPtatupnidehctaL

zHM76.61=qerFCIPAOI,dehctalsi"0"anehW

zHM3.33=qerFCIPAOI,dehctalsi"1"nehW

.pu-lluplanretniK06asahnipsihT

0FERTUO.tuptuokcolcecnereferzHM813.41,V3.3

31XNI

kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

42XTUO

daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC

)Fp33(pac

,32,71,41,6,5

74,14,53,42

)5:0(DNGRWPylppusV3.3rofsnipdnuorG

7,8]0:1[66V3TUOBUHrofstuptuokcolczHM66dexiFV3.3

,12,01,9,2

44,83,33,72,22

)5:0(DDVRWPylppusrewopV3.3

,61,81,91,02

11,21,31,51

]0:7[KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

62,52)1:0(zHM84TUOBSUrofstuptuokcolczHM84dexiFV3.3

92,82)1:0(SFNI

tuptuolla,ycneuqerfUPCsenimreteD.sniptceleSnoitcnuF

.3egapnoelbatytilanoitcnuFotreferesaelP.ytilanoitcnuf

03ATADSNIIroftupniataD

2

.tupnilairesC

13KLCSNIIfotupnikcolC

2

tupniC

23#DPNI

ecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA

ehtdnadelbasideraskcolclanretniehT.etatsrewopwolaotni

nwodrewopehtfoycnetalehT.deppotseralatsyrcehtdnaOCV

.sm3nahtretaergebtonlliw

,24,04,93,73,63

64,54,34

]0:7[MARDSTUO

denrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3

Ihguorhtffo

2

C

43F_MARDSTUOIybdetceffatonMARDSzHM001gninnureerfV3.3

2

C

84,65]0:1[LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG

25,05,94]0:2[KLCUPCTUO

SFnognidnepedzHM001rozHM66.tuptuokcolcsubtsoHV5.2

.3egaprefeRsnip)1:0(

35,15)1:0(LDDVRWPCIPAOI&UPCrofylppyusrewopV5.2
55,45]0:1[CIPAOITUO.zHM3.33rozHM76.61tagninnurstuptuokcolcV5.2

3

ICS9250-10

Preliminary Product Preview

Functionality Table

1SF0SFUPCMARDS66V3KLCICPzHM840FERCIPAOIsetoN

00 Z-iHZ-iHZ-iHZ-iHZ-iHZ-iHZ-iHetatsirT
01 2/KLCT4/KLCT4/KLCT8/KLCT2/KLCTKLCT61/KLCTedoMtseT

10 zHM66zHM001zHM66zHM33zHM84zHM813.41zHM76.61
11 zHM001zHM001zHM66zHM33zHM84ZHM813.41zHM76.61

Select Functions

#DPKLCUPCMARDSCIPAOIzHM66KLCICP

,FER

zHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLFFOFFO

1NONONONONONONONO

1SF0SFsetoN

00 etatsirT
01 edoMtseT

10 zHM66=UPCevitcA
11 zHM001=UPCevitcA

Clock Enable Configuration

4

ICS9250-10

Preliminary Product Preview

Power Down Waveform

Note

1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all

the output clocks are driven Low on their next High to Low tranistiion.

2. Power-up latency <3ms.

3. Waveform shown for 100MHz

E018

noitidnoC

noitpmusnocylppusV5.2xaM

,sdaolpacetercsidxaM

V526.2=2qddV

DNGro3qddV=stupnicitatsllA

noitpmusnocylppusV5.2xaM

,sdaolpacetercsidxaM

V564.3=2qddV

DNGro3qddV=stupnicitatsllA

edoMnwodrewoP

0=#NWDRWP(

Am01Am01

zHM66evitcAlluF

01=0,1LES

Am07Am082

zHM001evitcAlluF

11=0,1LES

Am001Am082

Maximum Allowed Current

5

ICS9250-10

Preliminary Product Preview

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controler (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write: