ICST AV9248F-90-T, ICS9248F-90-T Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9248-90

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

9248-90 Rev C 4/19/00

Pin Configuration

• 3.3V outputs: SDRAM, PCI, REF , 48/24MHz

• 2.5V outputs: CPU, IOAPIC

• 20 ohm CPU clock output impedance

• 20 ohm PCI clock output impedance

• Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns, center 2.6 ns.

• No external load cap for CL=18pF crystals

• ±175 ps CPU clock skew

• 250ps (cycle to cycle) CPU jitter

• Smooth frequency switch, with selections from 66.8 to 133 MHz CPU.

•I

C interface for programming

• 3ms power up clock stable time

• Clock duty cycle 45-55%.

• 48 pin 300 mil SSOP package

• 3.3V operation, 5V tolerant inputs (with series R)

• <5ns propagation delay SDRAM from Buffer Input

48-Pin SSOP

Power Groups

VDDREF = REF (0:1), X1, X2 VDDPCI = PCICLK_F , PCICLK(0:4) VDDSDR = SDRAM (0:12), supply for PLL core VDD48 = 24MHz, 48MHz VDDLIOAPIC = IOAPIC VDDLCPU = CPUCLK 1, CPUCLK_F

* Internal Pull-up Resistor of 240K to VDD ** Internal Pull-down resistor of 240K to GND

The ICS9248-90 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions.

Features include two CPU, six PCI and thirteen SDRAM clocks. T wo reference outputs are available equal to the crystal frequency. Plus the IOAPIC output powered by VDDL1. One 48 MHz for USB, and one 24 MHz clock for Super IO. Spread Spectrum built in at ±0.25% modulation to reduce the EMI. Serial programming I2C interface allows changing functions, stop clock programing and Frequency selection. Additionally , the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. It is not recommended to use I/O dual function pin for the slots (ISA, PIC, CPU, DIMM). The add on card might have a pull up or pull down.

High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50 ±5% duty cycle. The REF and 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates into 20pF.

CPU_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz 24MHz

IOAPIC

CPUCLK_F

CPUCLK 1

SDRAM (0:11)

PCICLK (0:4) PCICLKF

SDRAM_F

BUFFER IN

XTAL OSC

PCI CLOCK DIVDER

STOP

SDATA

SCLK

FS(0:3)

MODE

Control

Logic

Config.

Reg.

REF(0:1)

LATCH

POR

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9248-90

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low .

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ICS9248-90

Functionality

VDD = 3.3V±5%, V

DDL

= 2.5V±5% T A=0 to 70°C

Crystal (X1, X2) = 14.31818MHz

Mode Pin - Power Management Input Control

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00000 28.6604.33 00001 10.8600.43 00010 99.1799.53 00011 00.5794.73 00100 00.8799.83 00101 00.0899.93 00110 00.2800.14 00111 00.3805.14 01000 00.4899.14 01001 10.5805.24 01010 19.5859.24 01011 99.6894.34 01100 00.8899.34 01101 10.9805.44 01110 00.0999.44 01111 99.0994.54 10000 99.1966.03 10001 70.3920.13 10010 00.4933.13 10011 00.5966.13 10100 00.6999.13 1010 1 10.7933.23 10110 10.8976.23 10111 99.8999.23 11000 32.00114.33 11001 20.20110.43 11010 00.40166.43 11011 00.60133.53 11100 10.80100.63 11101 99.90166.63 11110 00.42199.03 11111 99.23152.33

ICS9248-90

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

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3tiB

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ICS9248-90

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR( 6tiB71 )tcanI/tcA(F_KLCICP 5tiB-1 )devreseR( 4tiB411 )tcanI/tcA(4KLCICP 3tiB211 )tcanI/tcA(3KLCICP 2tiB111 )tcanI/tcA(2KLCICP 1tiB011 )tcanI/tcA(1KLCICP 0tiB81 )tcanI/tcA(0KLCICP

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X #2SFdehctaL 6tiB-X #4SFdehctaL 5tiB-1 )devreseR( 4tiB-1 )devreseR( 3tiB041 )tcanI/tcA(21MARDS 2tiB-1 )devreseR( 1tiB341 )tcanI/tcA(1KLCUPC 0tiB441 )tcanI/tcA(F_KLCUPC

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X#EDOM 6tiB-X #0SFdehctaL 5tiB621 )tcanI/tcA(zHM84 4tiB521 )tcanI/tcA(zHM42 3tiB-1 )devreseR( 2tiB71,81,02,121 )evitcanI/evitcA()11:8(MARDS 1tiB82,92,13,231 )evitcanI/evitcA()7:4(MARDS 0tiB43,53,73,831 )evitcanI/evitcA()3:0(MARDS

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