Datasheet AV9248F-90-T, ICS9248F-90-T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9248-90

Block Diagram

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

TM

9248-90 Rev C 4/19/00

Pin Configuration

• 3.3V outputs: SDRAM, PCI, REF , 48/24MHz

• 2.5V outputs: CPU, IOAPIC

• 20 ohm CPU clock output impedance

• 20 ohm PCI clock output impedance

• Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.

• No external load cap for CL=18pF crystals

• ±175 ps CPU clock skew

• 250ps (cycle to cycle) CPU jitter

• Smooth frequency switch, with selections from 66.8
to 133 MHz CPU.

•I

2

C interface for programming

• 3ms power up clock stable time

• Clock duty cycle 45-55%.

• 48 pin 300 mil SSOP package

• 3.3V operation, 5V tolerant inputs (with series R)

• <5ns propagation delay SDRAM from Buffer Input

48-Pin SSOP

Power Groups

VDDREF = REF (0:1), X1, X2
VDDPCI = PCICLK_F , PCICLK(0:4)
VDDSDR = SDRAM (0:12), supply for PLL core
VDD48 = 24MHz, 48MHz
VDDLIOAPIC = IOAPIC
VDDLCPU = CPUCLK 1, CPUCLK_F

* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND

The ICS9248-90 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.

Features include two CPU, six PCI and thirteen SDRAM
clocks. T wo reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.25% modulation to reduce the EMI.
Serial programming I2C interface allows changing functions,
stop clock programing and Frequency selection. Additionally ,
the device meets the Pentium power-up stabilization, which
requires that CPU and PCI clocks be stable within 2ms after
power-up. It is not recommended to use I/O dual function pin
for the slots (ISA, PIC, CPU, DIMM). The add on card might
have a pull up or pull down.

High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 50 ±5% duty cycle. The REF and 24 and
48 MHz clock outputs typically provide better than 0.5V/ns
slew rates into 20pF.

CPU_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz
24MHz

IOAPIC

CPUCLK_F

CPUCLK 1

SDRAM (0:11)

PCICLK (0:4)
PCICLKF

SDRAM_F

X1

X2

BUFFER IN

XTAL
OSC

PCI
CLOCK
DIVDER

STOP

STOP

STOP

STOP

SDATA

SCLK

FS(0:3)

MODE

Control

Logic

Config.

Reg.

/2

REF(0:1)

LATCH

POR

2

12

5

4

4

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-90

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low .

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sdaolSUBASIrofreffub

#POTS_ICP

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nI(woltupninehw,level0cigoltaskcolc)4:0(KLCICPstlaH

)0=EDOM,edomelibom

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54,93,33

DNGRWPdnuorG

41XNI

kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

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daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC

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rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

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3

ICS9248-90

Functionality

VDD = 3.3V±5%, V

DDL

= 2.5V±5% T A=0 to 70°C

Crystal (X1, X2) = 14.31818MHz

Mode Pin - Power Management Input Control

7niP,EDOM

)tupnIdehctaL(

2niP

0

#POTS_ICP

)tupnI(

1

0FER

)tuptuO(

4SF3SF2SF1SF0SFzHMUPCzHMICP

00000 28.6604.33
00001 10.8600.43
00010 99.1799.53
00011 00.5794.73
00100 00.8799.83
00101 00.0899.93
00110 00.2800.14
00111 00.3805.14
01000 00.4899.14
01001 10.5805.24
01010 19.5859.24
01011 99.6894.34
01100 00.8899.34
01101 10.9805.44
01110 00.0999.44
01111 99.0994.54
10000 99.1966.03
10001 70.3920.13
10010 00.4933.13
10011 00.5966.13
10100 00.6999.13
1010 1 10.7933.23
10110 10.8976.23
10111 99.8999.23
11000 32.00114.33
11001 20.20110.43
11010 00.40166.43
11011 00.60133.53
11100 10.80100.63
11101 99.90166.63
11110 00.42199.03
11111 99.23152.33

4

ICS9248-90

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

tiBnoitpircseDDWP

tiB

)4:7,2(

)4:7,2(tiB

KLCUPC

zHM

KLCICP

zHM

XXX

1etoN

00000 28.6604.33
00001 10.8600.43
00010 99.1799.53
00011 00.5794.73
00100 00.8799.83
00101 00.0899.93
00110 00.2800.14
00111 00.3805.14
01000 00.4899.14
01001 10.5805.24
01010 19.5859.24
01011 99.6894.34
01100 00.8899.34
01101 10.9805.44
01110 00.0999.44
01111 99.0994.54

10000 99.1966.03
10001 70.3920.13
100 10 00.4933.13
100 11 00.5966.13
10100 00.6999.13
1010 1 10.7933.23
10110 10.8976.23
10111 99.8999.23
11000 32.00114.33
11001 20.20110.43
11010 00.40166.43
11011 00.60133.53
11100 10.80100.63
11101 99.90166.63
11110 00.42199.03
11111 99.23152.33

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

2,4:7tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

elbanemurtcepsdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

5

ICS9248-90

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB71 )tcanI/tcA(F_KLCICP
5tiB-1 )devreseR(
4tiB411 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X #2SFdehctaL
6tiB-X #4SFdehctaL
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB041 )tcanI/tcA(21MARDS
2tiB-1 )devreseR(
1tiB341 )tcanI/tcA(1KLCUPC
0tiB441 )tcanI/tcA(F_KLCUPC

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X#EDOM
6tiB-X #0SFdehctaL
5tiB621 )tcanI/tcA(zHM84
4tiB521 )tcanI/tcA(zHM42
3tiB-1 )devreseR(
2tiB71,81,02,121 )evitcanI/evitcA()11:8(MARDS
1tiB82,92,13,231 )evitcanI/evitcA()7:4(MARDS
0tiB43,53,73,831 )evitcanI/evitcA()3:0(MARDS

6

ICS9248-90

Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-X #1SFdehctaL
2tiB-1 )devreseR(
1tiB-X #3SFdehctaL
0tiB-1 )devreseR(

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB741 )tcanI/tcA(0CIPAOI
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB641 )tcanI/tcA(1FER
0tiB21 )tcanI/tcA(0FER

7

ICS9248-90

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature. . . . . . . . . . . . 0°C to +70°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

Electrical Characteristics - Input/Suppl y/Common Out put Parameters

TA = 0 - 70º C; Supply Voltage V

DD, VDDL

= 3.3 V +/-5% (unl e ss otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High V oltage V

IH

2V

DD

+0.3 V

Input L ow Volta ge V

IL

VSS-0.3 0.8 V

Inpu t High Current I

IH

VIN = V

DD

0.1 5

µ

A

Input Low Current I

IL1

VIN = 0 V; Inpu ts with no pul l-up resistors -5 2.0

µ

A

Input Low Current I

IL2

VIN = 0 V; Inpu ts with pull-up r esistors -200 -100

µ

A

I

DD3.3OP66CL

= 0 pF; Sel ect @ 66MHz 87

I

DD3.3OP100CL

= 0 pF; Sel ect @ 100MHz 120

I

DD3.3OP124CL

= 0 pF; Sel ect @ 124MHz 144

I

DD3.3OP133CL

= 0 pF; Sel ect @ 133MHz 149

Input freque nc y F

i

VDD = 3.3 V 12 14.318 16 MH z

Input Capacita nce

1

C

IN

Logic Inputs 5 pF

C

INX

X 1 & X2 pins 27 36 45 pF

Clk Stabiliza tion

1

T

STAB

From VDD = 3.3 V to 1% tar get Freq.

3ms

1

G ua ranteed by de sign, not 100 % t ested in production.

Operating

Suppl y C urre nt

mA180

170 mA

Electrical Charact eristics - Input/Supply/Com m on Output Paramet ers

TA = 0 - 70º C; Supply V oltage VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5% (unless other wi se stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

I

DD2.5OP66

CL = 0 pF; Select @ 66.8 MHz 7 30

Operating I

DD2.5OP100

CL = 0 pF; Select @ 100 MHz 10 30

Supply Current I

DD2.5OP124

CL = 0 pF; Select @ 124 MHz 11 30

I

DD2.5OP133

CL = 0 pF; Select @ 133 MHz 14 30

Skew

1

t

CPU-P CI

VT = 1.5 V; VTL = 1.25 V

1.5 2.7 4 ns

1

Guaranteed by design, not 100% tested in produ c t ion.

mA

8

ICS9248-90

Ele ctrical C haracteristics - CPUCLK

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unle ss otherwise state d )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V

OH2B

IOH = -12.0 mA 2 2. 3 V

Output Low Voltage V

OL2B

IOL = 12 mA 0.31 0.4 V

O utput High Cur rent I

OH2B

VOH = 1 .7 V -36 -19 mA

Ou tput Low Current I

OL2B

VOL = 0.7 V 19 26 mA

Rise Time t

r2B

1

VOL = 0.4 V, VOH = 2 .0 V 1.1 1.6 ns

Fall Time t

f2B

1

VOH = 2.0 V, VOL = 0 .4 V 1.1 1.6 ns

Duty Cycle d

t2B

1

VT = 1.25 V, Freq. < 124 MH z 45 49 55 %
V

T

= 1.25 V, Freq. >= 124 MHz 40 47 52 %

Skew t

sk2B

1

VT = 1.25 V 115 175 ps

Jitter, One Sigma t

j1σ2B

1

VT = 1.25 V 36 150 ps

Jitter, Absolute t

jabs2B

1

VT = 1.25 V -2 50 130 +250 ps

Jitter, Cycle- to-cycle

t

jcyc-cyc2B

1

VT = 1.25 V

140 250 ps

1

G ua ranteed by d e sign, not 100% tested i n production.

Ele ctrical C haracterist ics - SDRA M

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 30 pF (unle ss otherwise state d )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High Voltage V

OH3

IOH = -25 mA 2.4 2.85 V

Output Low Voltage V

OL3

IOL = 20 mA 0.35 0.4 V

O utput High Cur rent I

OH3

VOH = 2 .0 V -60 -40 mA

Ou tput Low Current I

OL3

VOL = 0.8 V 41 44 mA

Rise Time T

r3

1

VOL = 0.4 V, VOH = 2 .4 V 1.5 2.4 ns

Fall Time T

f3

1

VOH = 2.4 V, VOL = 0 .4 V 1.6 2.2 ns

Duty Cycle D

t3

1

VT = 1.5 V 455155%

Skew

1

T

sk1

VT = 1.5 V 220 500 ps

Propagation Delay Tprop

V

T

= 1.5 V

2.8 4 ns

1

G ua renteed by d e sign, not 100% tested i n production.

9

ICS9248-90

Electrical Characteristics - PCICLK

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 30 pF (unle ss otherwise state d )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Hi gh Voltage V

OH1

IOH = -11 mA 2.4 3.1 V

Output Low V oltage V

OL1

IOL = 9.4 mA 0.17 0.4 V

Ou tput Hi gh Cur rent I

OH1

VOH = 2.0 V -60 -22 mA

Output Low Current I

OL1

VOL = 0.8 V 25 44 mA

Rise Time

1

t

r1

VOL = 0.4 V, VOH = 2.4 V 1.87 2.6 ns

Fall Time

1

t

f1

VOH = 2.4 V , VOL = 0.4 V 1.5 2.3 ns

Duty Cycle

1

d

t1

VT = 1.5 V 45 49 55 %

Skew

1

t

sk1

VT = 1.5 V 124 500 ps

Jitter, One Si gma

1

t

j1σ1

VT = 1.5 V 70 150 ps

Jitter, Absolute

1

t

jabs1

VT = 1.5 V -500 160 500 ps

Jitter, Cycle-to-cycle

1

t

jcyc-cyc1

VT = 1.5 V

130 400 ps

1

Guaranteed by design, not 100% tested in pr oduc t ion.

Ele ctrical Characteris tics - IOAPIC

TA = 0 - 70º C; VDD = 3.3 V + /-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stat e d)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output High V oltage V

OH4BIOH

= -8 mA 2 2.3 V

Output Low V oltage V

OL4BIOL

= 12 mA 0.31 0.4 V

Ou tput Hi gh Current I

OH4B

VOH = 1.7 V -25 -15 mA

O ut put Low Current I

OL4B

VOL = 0.7 V 19 27 mA

Rise Time

1

T

r4B

VOL = 0.4 V , VOH = 2.0 V 1.4 2.2 ns

Fall Time

1

T

f4B

VOH = 2.0 V, VOL = 0.4 V 1.3 2 ns

Duty Cycle

1

D

t4B

VT = 1.25 V 45 52 55 %

Jitter, One Sigma

1

T

j1σ4B

VT = 1.25 V 175 350 ps

Jitter, Absolute

1

T

jabs4B

VT = 1.25 V -800 395 800 ps

Jitter, Cycle- to- cyc le

1

t

jcyc-cyc4BVT

= 1.25 V

475 800 ps

1

Guaranteed by de sign, not 100% tested in pro duction.

10

ICS9248-90

Ele ctrical C haracteristics - REF1:0

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unle ss otherwise state d )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Hi gh Voltage V

OH5

IOH = -12 mA 2.4 2.9 V

Output Low V oltage V

OL5

IOL = 10 mA 0.33 0.4 V

Ou tput Hi gh Cur rent I

OH5

VOH = 2.0 V -30 -22 mA

Output Low Current I

OL5

VOL = 0.8 V 16 23 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 2.1 4 ns

Fall Time

1

t

f5

VOH = 2.4 V , VOL = 0.4 V 2.1 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 52 55 %

Jitter, One Si gma

1

t

j1σ5

VT = 1.5 V 200 400 ps

Jitter, Absolute

1

t

jabs5

VT = 1.5 V -800 520 800 ps

Jitter, Cycle-to-cycle

1

t

jcyc-cyc5

VT = 1.5 V

790 1300 ps

1

Guaranteed by design, not 100% tested in produ c t ion.

Ele ctrical C haracterist ics - 24MH z, 48MH z

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unle ss otherwise state d )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

O utput Hi gh Voltage V

OH5

IOH = -12 mA 2.4 2.9 V

Output Low V oltage V

OL5

IOL = 12 mA 0.3 0.4 V

Ou tput Hi gh Cur rent I

OH5

VOH = 2.0 V -34 -22 mA

Output Low Current I

OL5

VOL = 0.8 V 16 30 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 1.6 4 ns

Fall Time

1

t

f5

VOH = 2.4 V , VOL = 0.4 V 1.7 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 51.6 55 %

Jitter, One Si gma

1

t

j1σ5

VT = 1.5 V 100 400 ps

Jitter, Absolute

1

t

jabs5

VT = 1.5 V -800 250 800 ps

Jitter, Cycle-to-cycle

1

t

jcyc-cyc5

VT = 1.5 V

345 1000 ps

1

Guaranteed by design, not 100% tested in pr oduc t ion.

11

ICS9248-90

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controler (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write:

12

ICS9248-90

Fig. 1

Shared Pin Operation ­Input/Output Pins

The I/O pins designated by (input/output) on the ICS9248­90 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.

To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.

Via to
VDD

Clock trace to load

Series Term. Res.

Programming
Header

Via to Gnd

Device
Pad

2K 

8.2K 

Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.

13

ICS9248-90

CPU_STOP# Timing Diagram

CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-90. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is
less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.

Notes:

1. All timing is referenced to the internal CPU clock.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-90.

3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low.

4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-90
CPU_STOP# signal. SDRAM (0:11) are controlled as shown.

5. All other clocks continue to run undisturbed.

14

ICS9248-90

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the ICS9248-90. It is used to turn off the PCICLK (0:4) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-90 internally . The minimum that the PCICLK (0:4) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.

3. All other clocks continue to run undisturbed.

4. CPU_STOP# is shown in a high (true) state.

15

ICS9248-90

Connections to VDD:

General Layout Precautions:

1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces.

2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.

Notes:

1 All clock outputs should have

provisions for a 15pf capacitor
between the clock output and series
terminating resistor. Not shown in
all places to improve readability of
diagram.

2 Optional crystal load capacitors are

recommended. They should be
included in the layout but not
inserted unless needed.

C1

C1

2

C3

1

Clock Load

C3

C3

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

3

4

5

6

7

8

Ferrite
Bead

VDD

C2

22µF/20V

Tantalum

Ferrite
Bead

VDD

C2

22µF/20V

Tantalum

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

= Routed Power

= Ground Connection Key (component side copper)

= Ground Plane Connection

= Power Route Connection

= Solder Pads

= Clock Load

Ground

2.5V Power Route

3.3V Power Route

3.3V Power Route

16

ICS9248-90

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

Ordering Information

ICS9248yF-90-T

Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)
Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T