ICST AV9248F-77, ICS9248F-77 Datasheet

Integrated Circuit Systems, Inc.

General Description

ICS9248-77

Block Diagram

Frequency Timing Generator for PENTIUM II Systems

9248-77 Rev C 10/20/99

Pin Configuration

48-pin SSOP

*120K ohm pull-up to VDD on indicated inputs.

 Generates the following system clocks:

- 3 - CPUs @ 2.5V, up to 150MHz.

- 3 - IOAPIC @ 2.5V, PCI or PCI/2

- 3 - 3V66MHz @ 3.3V.

- 11 - PCIs @ 3.3V.

- 1 - 48MHz, @ 3.3V fixed.

- 1 - 24MHz, @ 3.3V fixed.

- 1 - CPU/2, @ 2.5V.

 ± .25% center spread, or 0 to -.5% down spread.  Uses external 14.318MHz crystal.

The ICS9248-77 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the ICS9212-01.

Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248- 77 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

The CPU/2 clocks are inputs to the DRCG.

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

Features

Key Specification

 CPU Output Jitter: <250ps  CPU/2 Output Jitter. <250ps  IOAPIC Output Jitter: <500ps  48MHz, 3V66, PCI Output Jitter: <500ps  Ref Output Jitter. <1000ps  CPU Output Skew: <175ps  IOAPIC Output Skew <250ps  PCI Output Skew: <500ps  3V66 Output Skew <250ps  CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)  3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)  CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)

ICS9248-77

Pin Descriptions

Pi n n umber Pi n n ame Type Desc ription

1, 7, 13, 19, 25, 31 GND PWR Ground pins

2 REF0 OUT 14.318MHz reference clock outputs at 3.3V

REF1 OUT 14.318MHz reference clock outputs at 3.3V SEL24_48 IN Logic input to select 24 or 48MHz for pin 26 output

4, 10, 16, 23,

28, 35

VDD PWR Power pins 3.3V

5 X1 IN XTAL_IN 14.318MHz crystal input 6 X2 OUT XTAL _OUT C rystal output

PCICLK_F OUT

Free running PC I c l oc k at 3.3V. Sync hro nous to C PU cl ocks. Not affected b

the PCI_STOP# i nput. FS0 IN Logi c - input for frequency se l ection PCICLK 1 OUT PCI clock output at 3.3V. Synch ronous to C PU c l ocks. FS1 IN Logi c - input for frequency se l ection PCICLK 2 OUT PCI clock output at 3.3V. Synch ronous to C PU c l ocks. FS2 IN Logi c - input for frequency se l ection PCICLK 3 OUT PCI clock output at 3.3V. Synch ronous to C PU c l ocks. FS3 IN Logi c - input for frequency se l ection

14, 15, 17, 18 , 2 0 ,

21, 22

PCICLK [4:10] OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24 PD# IN

This asynchronous input powers down the chip when drive active(Low). The internal PLLs are disabled and all the output clocks are held at a Low state.

24_48MHz OUT

24 or 48MHz ou tp ut sel ectable by SEL24_48# (0=48MHz 1=24MHz)

FRE Q_ A PIC IN L o g i c input for fre q u ency sele ction of IOA PIC

27 48MHz/SEL_3V66 OUT/IN

Fixed 48MHz clock output. 3.3V / Logic input to select the fre

uency of the 3V66 ou tputs

29 SCLK IN

Clock in

ut of I2C inpu

30 SDATA IN

Data in

ut for I2C serial input.

32, 33, 34 3V66[0:2] OUT

3.3V clock outputs. These outputs are stopped when CPU_STOP# is driven active..

36 GNDLCPU PWR Ground pin for the CPUCLKs

37, 38, 40 CPUCLK[0:2] OUT Host bus clock output at 2.5V.

39 VDDLCPU PWR Power pin for the CPUCLKs. 2.5V 41 GNDLCPU/2 PWR Ground pin for the CPU/2 clocks. 42 CPU/2 OUT 2.5V clock outputs at 1/2 CPU frequency. 43 VDDL C PU/2 PWR Power pin for the CPU/2 clocks. 2.5V 45 GNDLIOAPIC PWR Ground pin for the IOAPIC outputs.

44, 46, 47 IOAPIC[0:2] OUT IOAPIC clocks at 2.5V. Synchronous with CPUCLKs

48 VDDLIOAPIC PWR Power pin for the IOAPIC outputs. 2.5V.

Power Groups:

VDDREF, GNDREF = REF, X1, X2 GNDPCI, VDDPCI = PCICLK VDD66, GND66 = 3V66 VDD48, GND48 = 48MHz VDDCOR, GNDCOR = PLL Core VDDLCPU/2 , GNDLCPU/2 = CPU/2 VDDLIOAPIC, GNDIOAPIC = IOAPIC

ICS9248-77

Note:

* These output frequencies are Not synchronous to CPUCLK and Do Not have Spread Spectrum modulation.

Frequency Selection

3SF2SF1SF0SF

UPC

zHM

2/UPC

zHM

ICP

zHM

zHM66V3zHMCIPAOI

0=66V3_LES1=66V3_LES0=CIPA_QERF1=ICPA_QERF 0000 5015.255307075.7153 0001 575.735.73*465757.815.73 0010 3.00151.054.336.666.667.614.33 0011 8.664.334.336.666.6676.614.33 0100 011556.63*463.373.816.63 0101 5115.753.83*466.6761.913.83 0110 7115.8593*46875.9193 0111 0210604*46080204

1000 5215.266.14*463.388.026.14 100 1 7215.363.24*466.4861.123.24 10 10 3.3315.663.336.666.666.613.33 10 11 5315.7657.335.765.768.6157.33 1100 7315.8652.435.865.86521.7152.43 1101 041075307075.7153 1110 5415.2752.63*465.27521.8152.63 1111 051575.73*465757.815.73

ICS9248-77

Power Management Features:

Note:

1. LOW means outputs held static LOW as per latency requirement next page.

2. On means active.

3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.

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.FER

zHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLWOLFFOFFO

1NONONONONONONONONO

Power Management Requirements:

Note:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/ high to the first valid clock comes out of the device.

2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.

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ICS9248-77

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.

Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.  Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge  Controller (host) sends a dummy command code  ICS clock will acknowledge  Controller (host) sends a dummy byte count  ICS clock will acknowledge  Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.  Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.  Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge  ICS clock will send the byte count  Controller (host) acknowledges  ICS clock sends first byte (Byte 0) through byte 5  Controller (host) will need to acknowledge each byte  Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit Address

(H)

Byte Count

ACK

Byte

ACK

Byte 1

ACK

Byte

ACK

Byte

ACK

Byte 4

ACK

Byte

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

(H)

Dummy Command Code

Dummy Byte Count

Byte 0

Byte 1

Byte 2

ACK

Byte 3

Byte 4

Byte 5

Stop Bit

How to Write:

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