ICST AV9248F-73, ICS9248F-73 Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9248-73

Block Diagram

Pentium II is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Timing Generator for Pentium II Systems

9248-73 Rev B 2/10/00

Pin Configuration

 Generates the following system clocks:

- 2 - CPUs @ 2.5V , up to 150MHz.

- 1 - IOAPIC @ 2.5V, PCI/2MHz.

- 9 - SDRAMs @ 3.3V, up to 150MHz.

- 2 - 3V66 @ 3.3V, 2x PCI MHz.

- 8 - PCIs @ 3.3V.

- 2 - 48MHz, @ 3.3V fixed.

- 1 - REF @ 3.3V, 14.318MHz.

- 1 - 24_48MHz, @ 3.3V fixed.

 Supports spread spectrum modulation ,

down spread 0 to -0.5%, ±0.25% center spread.

I

2

C support for power management
 Efficient power management scheme through PD#
 Uses external 14.138 MHz crystal

48-Pin 300 mil SSOP

The ICS9248-73 is a single chip clock for Intel Pentium II.
It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces EMI by 8dB to 10 dB.
This simplifies EMI qualification without resorting to board
design iterations or costly shielding. The ICS9248-73
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Power Groups

GNDREF, VDDREF = REF & Crystal
GND3V66, VDD3V66 = 3V66
GNDPCI, VDDPCI = PCICLK
GNDCOR, VDDCOR = PLL core
GND48, VDD48 = 48MHz
GNDSDR, VDDSDR = SDRAM
GNDLCPU, VDDLCPU = CPUCLK
GNDAPIC, VDDAPIC = IOAPIC

*120K ohm pull-up to VDD on indicated inputs.
**60K ohm pull-up to VDD on indicated inputs.

1. These pins will have 2x drive strength

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-73

Pin Descriptions

NIP

REBMUN

EMANNIPEPYTNOITPIRCSED

1

66V3_LESNI.ycneuqerftuptuo66V3ehtstcelesnipsihT

0FERTUO.tuptuokcolcecnereferzHM813.41,V3.3

,01,9,2

83,03,52,81

DDVRWPylppusrewopV3.3

31XNI

kcabdeefdna)Fp33(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

42XTUO

.zHM813.41yllanimon,tuptuolatsyrC

)Fp33(pacdaollanretnisaH

,12,41,6,5

,43,24,92

DNGRWPylppusV3.3rofsnipdnuorG

8,7)1:0(66V3TUOzHMICPX2tagninnurBUHrofstuptuokcolcV3.3

11

0KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

0SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

21

1KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

1SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

31

2KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

#84_42LESNI.tuptuotcelesottupnicigoL

,71,61,51

02,91

)7:3(KLCICPTUOSKLCUPCsuonorhcnyShtiw,stuptuokcolcICPV3.3

22#DPNI

otniecivedehtnwodrewopotdesuniptupniwolevitcasuonorhcnysA

dnaOCVehtdnadelbasideraskcolclanretniehT.etatsrewopwola

ebtonlliwnwodrewopehtfoycnetalehT.deppotseralatsyrceht

.sm3nahtretaerg

32KLCSNIIfotupnikcolC

2

tupniC

42ATADSNIIroftupniataD

2

.tupnilairesC

62

zHM84TUOBSUroftuptuokcolczHM84dexiFV3.3

3SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL

72zHM84TUOBSUroftuptuokcolczHM84dexiFV3.3

82

zHM84_42TUO.#84_42LESybdellortnoctuptuozHM84ro42

2SFNI.norewoptadehctaltupnI.tibtcelesycneuqerftupnicigoL
9284DNGRWPstuptuozHM84rofdnuorG
13F_MARDSTUOIybdetceffatonMARDSzHM001gninnureerfV3.3

2

C

,73,93,04,14
,23,33,53,63

)7:0(MARDSTUO

ffodenrutebnacstuptuoMARDSllA.zHM001gninnurtuptuoV3.3

Ihguorht

2

C

34LDNGRWPCIPA&UPCrofylppusrewopV5.2rofdnuorG

44,54)1:0(KLCUPCTUO

)3:0(SFnognidnepedzHM051otpu,tuptuokcolcsubtsoHV5.2

.3egaprefeRsnip

74CIPAOITUO.zHM2/ICPtagninnurstuptuokcolcV5.2

64,84LDDVRWPCIPAOI,UPCrofylppyusrewopV5.2

3

ICS9248-73

Clock Enable Configuration

#DPKLCUPCMARDSCIPAOIzHM66KLCICP

,FER

zHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLFFOFFO

1NONONONONONONONO

Frequency Selection

3SF2SF1SF0SF

UPC

zHM

MARDS

zHM

ICP

zHM

zHM66V3

zHMCIPAOI

0=66V3_LES1=66V3_LES
0000 32.00132.00114.3328.6628.6607.61
0001 09.00109.00136.3362.7662.7618.61
0010 00.50100.50100.5300.0700.0705.71
0011 98.6633.00144.3398.6698.6627.61
0100 00.02100.02100.04*00.4600.0800.02
0101 00.42100.42133.14*00.4666.2876.02
0110 03.33103.33134.44*00.4668.8812.22
0111 03.33103.33123.3356.6656.6666.61

1000 00.04100.04100.5300.0700.0705.71
100 1 00.05100.05105.73*00.4600.5757.81
10 10 99.41199.41133.83*00.4666.6761.91
10 11 00.0700.50100.5300.0700.0705.71
1100 00.5705.21105.73*00.4600.5757.81
1101 13.3869.42156.14*00.4613.3838.02
1110 00.0900.0900.0300.0600.0600.51
1111 00.5900.5976.1333.3633.3638.51

Note:
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.

4

ICS9248-73

Byte 0: Functionality and frequency select register (Default=0)
(1 = enable, 0 = disable)

tiB

noitpircseD

DWP

7tiB

murtcepSdarepSretneC%52.0±-0

%5.0-ot0murtcepSdaerpSnwoD-1

0

tiB

)4:6,2(

tiB

)4:6,2(

KLCUPC

zHM

MARDS

zHM

KLCICP

zHM

zHM66V3

zHMCIPAOI

0=66V3_LES1=66V3_LES

XXXX

1etoN

000032.00132.00114.3328.6628.6607.61

100009.00109.00136.3362.7662.7618.61

010000.50100.50100.5300.0700.0705.71

110098.6633.00144.3398.6698.6627.61

001000.02100.02100.04*00.4600.0800.02

101000.42100.42133.14*00.4666.2876.02

011003.33103.33134.44*00.4668.8812.22

111003.33103.33123.3356.6656.6666.61

000100.04100.04100.5300.0700.0705.71

100100.05100.05105.73*00.4600.5757.81

010199.41199.41133.83*00.4666.6761.91

110100.0700.50100.5300.0700.0705.71

001100.5705.21105.73*00.4600.5757.81

101113.3869.42156.14*00.4613.3838.02

011100.0900.0900.0300.0600.0600.51

111100.5900.5976.1333.3633.3638.51

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

4:6,2tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

elbanemurtcepsdaerpS-1

0

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

Notes:

1. Default at power-up will be for latched logic inputs to define frequency, Bit 2, 6:4 are default to 0000.
* These output frequencies are not synchronous to CPUCLK and do not have spread spectrum modulation.

5

ICS9248-73

Byte 1: Control Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured
at power-on and are not expected to be configured during the normal modes of operation.

2. PWD = Power on Default

tiB#niPDWPnoitpircseD

7tiB-X #3SF
6tiB-X #0SF
5tiB-X #2SF
4tiB821 zHM84-42
3tiB721 zHM84
2tiB621 zHM84
1tiB-0 )devreseR(
0tiB131 F_MARDS

tiB#niPDWPnoitpircseD

7tiB021 7KLCICP
6tiB911 6KLCICP
5tiB711 5KLCICP
4tiB611 4KLCICP
3tiB511 3KLCICP

2tiB31

1

2KLCICP

1tiB211 1KLCICP
0tiB111 0KLCICP

Byte 3: Control Register
(1 = enable, 0 = disable)

Byte 2: Control Register
(1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB231 7MARDS
6tiB331 6MARDS
5tiB531 5MARDS
4tiB631 4MARDS
3tiB731 3MARDS
2tiB931 2MARDS
1tiB041 1MARDS
0tiB141 0MARDS

tiB#niPDWPnoitpircseD

7tiB-0 )devreseR(
6tiB71 0_66V3
5tiB81 1_66V3
4tiB-X #66V3_LES
3tiB741 CIPAOI
2tiB-X #1SF
1tiB441 1KLCUPC
0tiB541 0KLCUPC

Byte 4: Control Register
(1 = enable, 0 = disable)