ICST AV9248F-66, ICS9248F-66 Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-66

Frequency Timing Generator for PENTIUM II Systems

9248-66 Rev - 7/28/99

Pin Configuration

48-pin SSOP

Features

 Generates the following system clocks:

- 3 CPU clocks ( 2.5V, 100/133MHz)

- 8 PCI clocks, including 1 free-running (3.3V, 33MHz)

- 1 CPU/2 clocks (2.5V, 50/66MHz)

- 1 IOAPIC clocks (2.5V, 16.67MHz)

- 3 Fixed frequency 66MHz clocks(3.3V, 66MHz)

- 2 REF clocks(3.3V, 14.318MHz)

- 1 USB clock (3.3V, 48MHz)

 Efficient power management through PD#, CPU_STOP#

and PCI_STOP#.

 0 to -0.5% typical down spread modulation on CPU,

PCI, IOAPIC, 3V66 and CPU/2 output clocks.

 Uses external 14.318MHz crystal.

Advance Information

ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.

Block Diagram

Key Specification

 CPU Output Jitter: <250ps
 CPU/2 Output Jitter. <250ps
 IOAPIC Output Jitter: <500ps
 48MHz, 3V66, PCI Output Jitter: <500ps
 Ref Output Jitter. <1000ps
 CPU Output Skew: <175ps
 PCI Output Skew: <500ps
 3V66 Output Skew <250ps
 CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
 3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
 CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)

2

ICS9248-66

Advance Information

Pin Descriptions

Power Groups:

VDDREF, GNDREF = REF, X1, X2
GNDPCI, VDDPCI = PCICLK
VDD66, GND66 = 3V66
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLIOAPIC, GNDIOAPIC = IOAPIC

The ICS9248-66 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9211-01.

Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI
by 8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9248-66 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process
and temperature variations.

The CPU/2 clocks are inputs to the DRCG.

General Description

Pin number Pin name Type Description

1, 7, 13, 19, 23, 26,

35

GND PWR Ground pins

2, 3 REF(0:1) OUT 14.318MHz reference clock outputs at 3.3V

4, 10, 16, 22, 28, 36 VDD PWR Power pins 3.3V

5 X1 IN XTAL_IN 14.318MHz crystal input
6 X2 OUT XTAL_OUT Crystal output

8 PCICLK_F OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not affected by the
PCI_STOP# in

p

ut.

9, 11, 12, 14,

15, 17, 18

PCICLK[1:7] OU T PCI clock outputs at 3.3V. Synchronous to CPU clocks.

20, 21, 24 3V66[0:2] OUT 66MHz outputs at 3.3V. These outputs are stopped when CPU_STO P# is driven active..

25 SEL 133/100# IN

This selects the frequency for the CPU and CPU/2 outputs. High = 133MHz,
Low=100MHz

27 48MHz OUT Fixed 48MHz clock output. 3.3V

29, 30 SEL[0:1] IN Function select pins. See truth table for details.

31 S PREAD# IN

Enables spread spectrum when active(Low ). modulates all the CPU, PCI , IOAPIC, 3V66
and CPU/2 clocks. Does not affect the REF and 48MHz clocks. 0.5% down spread
modulation.

32 PD# IN

This asynchronous input powers down the chip when drive active(Low). The internal PLLs
are disabled and all the o ut

p

ut clock s are held at a Low state.

33 CPU_STOP# IN

This asychronous input halts the CPUCLK[0:3] and the 3V66[0:3] clocks at logic "0"
wh en driven active( Low). Does not aff ect the CPU/2 clocks.

34 PCI_STOP# IN

This asynchronous input halts the PCICLK[1:7] at logic"0" when driven active(Low).
PC ICLK_F is n ot affected b

y

this input.

40 GN DLCPU PWR Ground pin for the CPUCLKs

37, 38, 41 CPUCLK[0:3] OUT

Host bus clock output at 2.5V . 133MHz or 100MHz depending on the state of the S EL
133/100MHz.

39, 42 VDDLCPU PWR Power pin for the CP UCLKs. 2.5V

43 GNDLCPU/2 PWR Ground pin for the CPU/2 clocks.
44 CPU/2 OUT

2.5V clock outputs at 1/2 CPU frequency. 66MHz or50MHz depending on the state of the
SEL 133/100# in

p

ut pin.
45 VDDLCPU/2 PWR Power pin for the CPU/2 clocks. 2.5V
46 G NDLIOAPIC PWR Ground pin for the IOAPIC outputs.
47 IOAPIC OUT IOAPIC clocks at 2.5V. Synchronous with CPUCLKs but fixed at 16.67MHz.

48 V DDLIOAPIC PWR Power pin for the IOAPIC outputs. 2.5V.

3

ICS9248-66

Advance Information

Frequency Select:

Note:

1. TCLK is a test clock driven on the x1 input during test mode.

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ICS9248-66 Power Management Features:

Note:

1. LOW means outputs held static LOW as per latency requirement next page.

2. On means active.

3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.

4. All 3V66 as well as all CPLU clocks should stop cleanly when CPU_STOP# is pulled LOW.

5. CPU/2, IOAPIC, REF, 48 MHz signals are not controlled by the CPU_STOP# functionality and are enabled all in all conditions
except PD# = LOW

4

ICS9248-66

Advance Information

Power Management Requirements:

Note:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.

2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.

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CPU_STOP# Timing Diagram

CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU and 3V66 clocks for low power
operation. CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI
clock (and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run
while the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse. ONLY one rising edge of PCICLK_F is allowed after the clock control logic
switched for both the CPU and 3V66 outputs to become enabled/disabled.

Notes:

1. All timing is referenced to the internal CPUCLK.

2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.

3. CPU_STOP# signal is an input singal that must be made synchronous to free running PCICLK_F

4. 3V66 clocks also stop/start before

5. PD# and PCI_STOP# are shown in a high state.

6. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz