ICST AV9248F-65, ICS9248F-65 Datasheet
Integrated
Circuit
Systems, Inc.
ICS9248-65
Third party brands and names are the property of their respective owners.
Block Diagram
Frequency Timing Generator for PENTIUM IISystems
9248-65 Rev C 7/28/99
Pin Configuration
48-pin SSOP
Generates the following system clocks:
- 3 CPU clocks ( 2.5V, 100/133MHz)
- 10 PCI clocks, including 1 free-running
(3.3V, 33.3MHz)
- 1 CPU/2 clocks (2.5V, 50/66.6MHz)
- 1 IOAPIC clocks (2.5V, 16.67MHz)
- 3 Fixed frequency 66MHz clocks(3.3V, 66.6MHz)
- 2 REF clocks(3.3V, 14.318MHz)
- 1 USB clock (3.3V, 48MHz)
Efficient power management through PD#.
0 to -0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
Uses external 14.318MHz crystal.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
Features
Key Specification
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
PCI Output Jitter. <500ps
Ref Output Jitter. <1000ps
CPU 0:2 Output Skew: <175ps
PCI_F, PCI 1:7 Output Skew: <500ps
3V66_0:2 Output Skew <250ps
CPU to 3V66_0:2 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4ns (CPU leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
2
ICS9248-65
Pin Descriptions
Pin number Pin name Type Description
1,2 REF Output 3.3V, 14.318 MHz re f e r e nce clock output.
3, 9, 17, 24,
28, 34
VDD Power 3.3 V power for clock outputs .
4 X1 Input 14.318 MHz cr ystal input
5 X2 Output 14.318 MHz cr ystal output
6,14, 20, 26,
33, 45, 48
GND Power Ground for cloc k outputs
7 PCICLK_F Output 3.3 V free running PCI clock output, will not be stopped by t he PCI_STOP#
8,10,11,12,13,
15,16,18,19
PCICLK (1:9) Output 3.3 V P C I cloc k outputs , generating timing r e quir ements f or
21,22, 23 3V66 Output 3.3 V 66 MHz c loc k output, fixed frequency cloc k typic al ly used with AGP
25
SEL
133/100#
Input
Control for the frequency of clocks a t the C PU output pins . If l ogic "0" is used the
100 MH z frequenc y is selecte d. If Logic "1" is used, the 133 MHz f requency is
sele c ted. The P C I clock is multiplexed to run a t 33. 3 M Hz f or both selecte d c a s e s .
27 48 MHz Output
3.3 V 48 MHz c loc k output, fixed frequency cloc k typic al ly used with USB
devices
29,30 SEL (0:1) Input Frequency se le ct pi n , logic input.
31 SPREAD# Output
Power-on spr ea d spectrum enable option. Active low = s pread spect rum clocking
enable. Active high = spre a d spectrum clocking disable .
32 PD# Input
Asynchronous ac t ive low input pin used to power down the device into a low
power s tate. The internal clocks are disabled and the V CO and the crystal ar e
stopped.
35,39 GNDLCPU Power Ground for the CPU and H ost clock outputs
36,37,40
CPUCLK
(0:2)
0utput 2.5 V CPU and H ost clock outputs
38,41 VDDLCPU Power 2.5 V powe r for the C PU and Host cloc k outputs
42 GNDLCPU/2 Powe r Ground for the CPU and Host cloc k outputs
43 CPU/2 Output Out put running at 1/2 CPU clock f requency. Synchronous to the C PU outputs .
44 VDDL C P U/2 Pow er 2.5 V pow e r f or the CPU/2 clock outputs
46 IOAPI C (0:1) Output 2.5V fixed 16. 6 M Hz IOA PIC cl ock outputs
47 VDDIOAPIC Power 2.5V power for IOAPIC clock
The ICS9248-65 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9211-01.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9248-65 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process
and temperature variations.
The CPU/2 clocks are inputs to the DRCG.
General Description Power Groups:
VDDREF, GNDREF = REF, X1, X2
GNDPCI, VDDPCI = PCICLK
VDD66, GND66 = 3V66
VDD48, GND48 = 48MHz
VDDCOR, GNDCOR = PLL Core
VDDLCPU/2 , GNDLCPU/2 = CPU/2
VDDLIOAPIC, GNDIOAPIC = IOAPIC
3
ICS9248-65
Frequency Select:
Note:
1. TCLK is a test clock driven on the x1 input during test mode.
ICS9248-65 Power Management Features:
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
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Power Management Requirements:
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
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