ICST AV9248F-39, ICS9248F-39 Datasheet
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9248-39
Block Diagram
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9248-39 Rev F 12/16/99
Pin Configuration
• 3.3V outputs: SDRAM, PCI, REF, 48/24MHz
• 2.5V outputs: CPU, IOAPIC
• 20 ohm CPU clock output impedance
• 20 ohm PCI clock output impedance
• Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns,
center 2.6 ns.
• No external load cap for CL=18pF crystals
• ±175 ps CPU clock skew
• 250ps (cycle to cycle) CPU jitter
• Smooth frequency switch, with selections from 66.8
to 150 MHz CPU.
•I
2
C interface for programming
• 3ms power up clock stable time
• Clock duty cycle 45-55%.
• 48 pin 300 mil SSOP package
• 3.3V operation, 5V tolerant inputs (with series R)
• <5ns propagation delay SDRAM from Buffer Input
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:12), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK 1, CPUCLK_F
* Internal Pull-up Resistor of 240K to VDD
** Internal Pull-down resistor of 240K to GND
The ICS9248-39 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel
PentiumPro or Cyrix. Eight different reference frequency
multiplying factors are externally selectable with smooth
frequency transitions.
Features include two CPU, six PCI and thirteen SDRAM
clocks. T wo reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at ±0.5% or ±0.25% modulation to reduce
the EMI. Serial programming I2C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be
stable within 2ms after power-up. It is not recommended to
use I/O dual function pin for the slots (ISA, PIC, CPU,
DIMM). The add on card might have a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK
outputs typically provide better than 1V/ns slew rate into 20pF
loads while maintaining 50±5% duty cycle. The REF and 24
and 48 MHz clock outputs typically provide better than 0.5V/
ns slew rates into 20pF.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-39
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
11DDVRWPV3.3lanimon,ylppusrewopLATX,)2:0(feR
2
0FERTUO
REGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41
sdaolSUBASIrofreffub
#POTS_ICP
1
NI
nI(woltupninehw,level0cigoltaskcolc)4:0(KLCICPstlaH
)0=EDOM,edomelibom
,22,61,9,3
54,93,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp63(pac
41,62DDVRWPV3.3lanimon,)4:0(KLCICPdnaF_KLCICProfylppuS
7
F_KLCICPTUO
rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF
.tnemeganam
EDOM
2,1
NI
.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf2niP
.tupnIdehctaL
8
3SFNIDNGotnwod-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF
0KLCICPTUO
wekssn84-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
31,21,11,01)4:1(KLCICPTUO
wekssn84-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP
)ylraeUPC(
51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
,12,02,81,71
,23,13,92,82
83,73,53,43
)0:11(MARDSTUO
nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS
.)tespihcybdellortnoc(
63,03,913DDVRWP.V3.3lanimon,eroCLLPUPCdna)21:0(MARDSrofylppuS
32ATADSNIIroftupniataD
2
tupnitnarelotV5,tupnilairesC
42KLCSNIIfotupnikcolC
2
tupnitnarelotV5,tupniC
52
zHM42TUOkcolctuptuozHM42
1SF
2,1
NI.tupnIdehctaL.niptcelesycneuqerF
62
zHM84TUOkcolctuptuozHM84
0SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
724DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
04F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF
14#POTS_UPCNI
MARDS&CIPAOI,1KLCUPCstlahtupnisuonorhcnysasihT
.wolnevirdnehwlevel"0"cigolta)11:0(
242LDDVRWPlanimonV3.3roV5.2rehtie,skcolcUPCrofylppuS
341KLCUPCTUOwoL=#POTS_UPCfiwoL.2LDDVybderewop,stuptuokcolcUPC
44F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF
64
1FERTUO.kcolcecnereferzHM813.41
2SF
2,1
NItupnIdehctaL.niptcelesycneuqerF
74CIPAOITUOCIPAOI.1LDDVybderewoPzHM813.41.tuptuokcolc
841LDDVRWPlanimonV3.3ro5.2rehtie,CIPAOIrofylppuS
3
ICS9248-39
Functionality
VDD1,2,3 = 3.3V±5%, V
DDL
1,2 = 2.5V±5% or 3.3±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz
Mode Pin - Power Management Input Control
7niP,EDOM
)tupnIdehctaL(
2niP
0
#POTS_ICP
)tupnI(
1
0FER
)tuptuO(
3SF2SF1SF0SF
UPC
)zHM(
)zHM(KLCICP
1111 331)4/UPC(3.33
1110 421)4/UPC(13
1101 051)4/UPC(5.73
1100 041)4/UPC(53
1011 501)3/UPC(53
1010 011)3/UPC(76.63
1001 511)3/UPC(33.83
1000 021)3/UPC(00.04
0111 3.001)3/UPC(34.33
0110 331)3/UPC(33.44
0101 211)3/UPC(33.73
0100 301)2/UPC(33.43
0011 8.66)2/UPC(04.33
0010 3.38)2/UPC(56.14
0001 57)2/UPC(5.73
0000 421)3/UPC(33.14
4
ICS9248-39
tiBnoitpircseDDWP
7tiB
noitaludoMmurtcepSdaerpS%52.0±-0
noitaludoMmurtcepSdaerpS%5.0±-1
0
4tiB5tiB6tiB2tiBkcolcUPCICP
1etoN
,2tiB
4:6tiB
1110
0110
3.001
331
)3/UPC(34.33
)3/UPC(33.44
1010
0010
211
301
)3/UPC(33.73
)3/UPC(3.43
1100
0100
8.66
3.38
)2/UPC(4.33
)2/UPC(56.14
1000
0000
57
421
)2/UPC(5.73
)3/UPC(33.14
1111
0111
331
421
)4/UPC(52.33
)4/UPC(00.13
1011
0011
051
041
)4/UPC(05.73
)4/UPC(00.53
1101
0101
501
011
)3/UPC(00.53
)3/UPC(76.63
1001
0001
511
021
)3/UPC(33.83
)3/UPC(00.04
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
)evoba(4:6tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
)daerpSretneC(delbanEmurtcepSdaerpS-1
0
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: PWD = Power-Up Default
Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6
are default to 000, and if bit 3 is written to a 1 to use Bits 6:4, then these should be
defined to desired frequency at same write cycle.
5
ICS9248-39
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB71 )tcanI/tcA(F_KLCICP
5tiB-1 )devreseR(
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-X #2SFdehctaL
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB041 )tcanI/tcA(21MARDS
2tiB-1 )devreseR(
1tiB341 )tcanI/tcA(1KLCUPC
0tiB441 )tcanI/tcA(F_KLCUPC
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
tiB#niPDWPnoitpircseD
7tiB-1 )devreseR(
6tiB-X #0SFdehctaL
5tiB621 )tcanI/tcA(zHM84
4tiB521 )tcanI/tcA(zHM42
3tiB-1 )devreseR(
2tiB71,81,02,121 )evitcanI/evitcA()11:8(MARDS
1tiB82,92,13,231 )evitcanI/evitcA()7:4(MARDS
0tiB43,53,73,831 )evitcanI/evitcA()3:0(MARDS
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