ICST AV9248F-157-T, ICS9248F-157-T Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-157

Third party brands and names are the property of their respective owners.

Block Diagram

9248-157 Rev A - 1/16/01

Functionality

Pin Configuration

28 Pin 209mil SSOP

Recommended Application:

ALI1621/1632M style chipsets

Output Features:

• 2 - CPUs @2.5V, up to 140MHz.

• 7 - PCI @3.3V, (including one free running)

• 1 - 48MHz, @3.3V fixed.

• 2 - REF @3.3V, 14.318MHz.

Features:

• Up to 140 MHz frequency support

• Support power management: CPU, PCI stop and
Power down.

• Spread spectrum for EMI control (0.5% down spread).

• Uses external 14.318MHz crystal

• FS pins for frequency select

Key Specifications:

• CPU – CPU: <175ps

• PCI – PCI: <250ps

• CPU(early)-PCI: 1.5ns - 4ns

• PCI_E (early) - PCI: 2.1ns

Frequency Timing Generator for Pentium II Systems

FS (3:0)

CPU_STOP#

X1
X2

OSC

PLL

Spread

Spectrum

Glitch

Free

Control

Logic

REF (1:0)

2

5

PCICLK (4:0),
PCICLK_E

48MHz

PCI_STOP#

SEL_CPUF#

PD#

Div4#

/4

BUS

STOP

PCICLK_F

PLL2

2

CPUCLK 1

CPUCLK0/F

CPU

STOP

CPU

STOP

/2

/3

SPREAD#

3SF2SF1SF0SFUPCICP

0000 33.3366.61

0001 33.3666.13

0010 99.9600.53

0011 66.6633.33

0100 00.7933.23

0101 22.6970.23

0110 05.1905.03

0111 33.3877.72

1000 00.0566.61

100 1 52.5957.13

10 10 00.50100.53

10 11 00.00133.33

1100 66.6666.61

110 1 53.62166.13

1110 56.93100.53

1111 33.33133.33

*These inputs have a 120K pull up to VDD
**These inputs have a 120K pull down to GND

*FS1/REF0

X1
X2

**FS2/PCICLK_F

*SEL_CPUF#/PCICLK0

PCICLK1

GND

VDDPCI
PCICLK2
PCICLK3
PCICLK4

PCICLK_E

VDD48

*FS3/48MHz

VDDR
REF1/FS0*
SPREAD#
VDDL
CPUCLK1
CPUCLK0/F
GNDL
GND
PCI_STOP#
VDDA
CPU_STOP#
PD#
DIV/4#
GND

ICS9248-157

1
2
3
4
5
6
7
8

9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is

2

ICS9248-157

Advance Information

Third party brands and names are the property of their respective owners.

Pin Descriptions

General Description

The ICS9248-157 is the Main clock solution for Notebook designs using the Intel ALI1621/1632M style chipset. Along with
an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system.

Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.
The ICS9248-157 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.

Pin number Pin name Type Description

FS1 Input Frequency selec t pin

REF0 Output 3.3V, 14.318 MHz reference clock output.

2 X1 Input 14.318 MHz crystal input
3 X2 Output 14.318 MHz crystal output

FS2 Input Frequency selec t pin

PCICLK _F Output 3.3 V free running PCI c lock output, will not be stopped by the PCI_STO P#

SEL_CPUF# Input

Active low input to select CPUCLK 0/F (pin 23) either normal CPUCLK or Free
running (not stoppable through CPU_STOP#) clock.

PCICLK 0 Output 3.3V P CI clock output

11, 10, 9, 6 PCICLK (4:1) Output 3.3 V PCI clock outputs, generating timing requirements

7, 15, 21 GND Power Ground for clock outputs

8 VDDPCI Power 3.3 V power for the PCI cloc k outputs
12 PCICLK_E Output Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
13 VDD48 Power 3.3 V power for 48 MHz clocks

FS3 Input Frequency selec t pin

48MHz Output Fixed 48MHz clock.

16 DIV 4# Input

Active low input, enables the CP UCLK and the P CICLK to run at 1/4 of the regular
frequecies

17 PD# Input

Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the V

CO

and the crystal are stopped. The

latency of the power down will not be greater than 3ms.

18 CP U_STOP # Input

Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.

19 VDDA Power 3.3 V power for the core

20 PCI-S TOP# Input

Synchronous ac tive low input used to stop the PCICLK in active low state. I t will not
effect PCICLK_F or any other outputs.

22 GNDL Power Ground for the CPU and Host cloc k outputs

23 CPUCLK0/F Output

2.5V CPU clock output; can be selected to be free running by driving

SEL_CPUF# low
24 CPUCLK1 0utput 2.5 V CP U and Host clock outputs
25 VDDL Power 2.5 V power for the CPU and Host clock outputs

26 S PREAD# Input

power-on spread spectrum enable option. Active low = spread spectrum c locking

enable. Ac tive high = spread spectrum clocking disable.

FS0 Input Frequency selec t pin

REF1 Output 3.3V, 14.318 MHz reference clock output.

28 V DDR Power 3.3 V power for the REFCLK and c rys tal clock outputs

14

1

27

4

5

3

ICS9248-157

Third party brands and names are the property of their respective owners.

Power Management

Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up
and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry.
Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.

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Power Groups:

VDDA = PLL Core
VDD48 = 48MHz Core
VDDPCI = PCICLK
VDDL = CPUCLK
VDDR = Xtal & REF

4

ICS9248-157

Advance Information

Third party brands and names are the property of their respective owners.

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V

DD

+0.5 V

Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.

Electrical Characteristics - Input/Sup ply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% VDDL = 2.5 V +/-5% (unless otherwise state

d)

PARAMETER

S

YMBOL

CO

NDITION

S

MIN TYP MAX UNIT

S

Input High Voltage V

IH

2V

DD

+0.3 V

Input Low Voltage V

IL

VSS-0.3 0.8 V

Input High Current I

IH

VIN = V

DD

0.1 5

µ

A

Input Low Current I

IL1

VIN = 0 V; Inputs with no pull-up resistors -5 2.0

µ

A

Input Low Current I

IL2

VIN = 0 V; Inputs with pull-up resistors -200 -100

µ

A

Operating I

DD3.3OP66CL

= 0 pF; Select @ 66MHz 60 180 mA

Supply Current I

DD3.3OP100CL

= 0 pF; Select @ 100MHz 66 180 mA

Power Down I

DD3.3PD

CL = 0 pF; With input address to Vdd or GND 70 600

µ

A

Supply Current

Input frequency F

i

VDD = 3.3 V; 11 14.318 16 MHz

Input Capacitance

1

C

IN

Logic Inputs 5 pF

C

INX

X1 & X2 pins 27 36 45 pF

Transition Time

1

T

trans

To 1st crossing of target Freq. 3 ms

Clk Stabilization

1

T

STAB

From VDD = 3.3 V to 1% target Freq. 3 ms

Sk

ew

1

T

CPU-PCI1

VT = 1.5 V;

1.5 2.3 4 ns

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5% (unless otherwise stated )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating I

DD2.5OP66

CL = 0 pF; Select @ 66.8 MHz 16 72 mA

Supply Current I

DD2.5OP100

CL = 0 pF; Select @ 100 MHz 23 100 mA

Skew

1

t

CPU-PCI2

VT = 1.5 V; VTL = 1.25 V

1.5 3 4 ns

1

Guaranteed by design, not 100% tested in production.