ICST AV9248F-151-T, ICS9248F-151-T Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-151

Third party brands and names are the property of their respective owners.

Block Diagram

9248-151 Rev B 01/29/01

Functionality

Pin Configuration

48-Pin 300mil SSOP

Recommended Application:

VIA Apollo Pro 266 style chipset.

Output Features:

• 3 - CPUs @ 2.5V, up to 200MHz.

• 3 - IOAPIC @ 2.5V, ½ PCI frequency

• 9 - PCI @ 3.3V,

• 1 - 48MHz, @ 3.3V fixed.

• 1 - 24/48MHz @ 3.3V

• 2 - REF @ 3.3V, 14.318MHz.

• 3 - AGP @ 3.3V

Features:

• Up to 200MHz frequency support

• Support power management: PCI, CPU stop
and Power Down.

• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU – CPU: <175ps

• PCI – PCI: <500ps

• CPU(early)-PCI: Min=1.0ns, Max=2.5ns

• CPU Cycle to cycle jitter: < 250ps

Frequency Generator & Integrated Buffers for Celeron & PII/III™

* Internal Pull-up Resistor of 120K to VDD

FS (4:0)

PD#

PCI_STOP#

CPU_STOP#

S DATA

SCLK

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK (1:0)

CPUCLK2/F

IOAPIC (2:0)

AGPCLK (2:0)

PCICLK (7:0)

8

3

3

2

2

PCICLK_F

X1

X2

XTAL

OSC

CPU

DIVDER

IOAPIC

DIVDER

AGP

DIVDER

PCI

DIVDER

Stop

Stop/F

Stop

Control

Logic

Config.

Reg.

/ 2

REF (1:0)

4SF3SF2SF1SF0SF

UPC

)zHM(

PGA

)zHM(

KLCICP

)zHM(
00000 00.00200.0800.04
00001 00.09100.6700.83
00010 00.08100.2700.63
00011 00.07100.8600.43
00100 00.66104.6602.33
00101 00.06100.4600.23
00110 00.05100.5705.73
00111 00.54105.2752.63
01000 00.04100.0700.53
01001 00.63100.8600.43
01010 00.03100.5605.23
01011 00.42100.2600.13
01100

76.6676.6643.33

01101

00.00176.6633.33

01110

00.81176.8733.93

01111

33.33176.6643.33

VDDREF

GND

X1
X2

AVDD48

*FS3/48MHz

*FS2/24_48MHz

GND

PCICLK_F

PCICLK0
PCICLK1

GND
PCICLK2
PCICLK3

VDDPCI
PCICLK4
PCICLK5
PCICLK6

GND

PCICLK7

*FS1
*FS0

AGPCLK0

VDDAGP

REF0
REF1/FS4*
VDDLAPIC
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDLCPU
GND
CPUCLK0
CPUCLK1
VDDLCPU
GND
CPUCLK2/F
CPU_STOP#*
PCI_STOP#*
PD*
AVDD
GND
S DATA
SCLK
AGPCLK2
AGPCLK1
GND

ICS9248-151

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-151

Third party brands and names are the property of their respective owners.

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic Hi to VDD or GND for logic low.

REBMUNNIPEMANNIPEPYTNOITPIRCSED

1FERDDVRWPV3.3lanimon,ylppusrewopLATX,feR

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34,04,63,03

DNGRWPdnuorG

31XNI

kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

42XTUO

daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC

)Fp63(pac

5zHM84DDVARWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
6

3SFNIDDVotpu-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF

zHM84TUOkcolctuptuozHM84

7

2SFNIDDVotpu-lluPlanretnI.tupnIdehctaL.niptcelesycneuqerF

zHM84_42TUOtuptuozHM84ro42

8zHM84DNGARWP.erocLLPdexifdnasreffubtuptuozHM84&42rofdnuorG
9F_KLCICPTUO

rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

.tnemeganam

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22,12)0:1(SF

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32,62,72)0:2(KLCPGATUO.deppotsebtonyamesehT.ICPX2sadenifedstuptuoPGA
42PGADDVRWPskcolcPGArofrewoP
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33#POTS_ICP

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74

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840FERTUO.kcolcecnereferzhM813.41

3

ICS9248-151

Third party brands and names are the property of their respective owners.

General Description

The ICS9248-151 is a single chip clock solution for Desktop
designs. It provides all necessary clock signals for such a
system.

Spread spectrum may be enabled through I

2

C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-151
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Serial programming I

2

C interface allows changing functions,

stop clock programming and frequency selection.

Power Groups

A VDD, AGND = Core PLL
A VDD48, AGND48 = 24, 48MHz and fixed PLL
VDDREF , GNDREF = REF clocks, Xtal

4

ICS9248-151

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3.

tiBnoitpircseDDWP

1,2tiB
4:6tiB

2tiB1tiB6tiB5tiB4tiB

KLCUPC

)zHM(

KLCPGA

)zHM(

KLCICP
)zHM(

CIPAOI
)zHM(

daerpS

egatnecerP

XXXX
1etoN

4SF3SF2SF1SF0SF
00000 00.00200.0800.0400.02%52.0-/+
00001 00.09100.6700.8300.91%52.0-/+
00010 00.08100.2700.6300.81%52.0-/+
00011 00.07100.8600.4300.71%52.0-/+
00100 00.66104.6602.3306.61%52.0-/+
00101 00.06100.4600.2300.31%52.0-/+
00110 00.05100.5705.7357.81%52.0-/+
00111 00.54105.2752.6321.81%52.0-/+
01000 00.04100.0700.5305.71%52.0-/+
01001 00.63100.8600.4300.71%52.0-/+
01010 00.03100.5605.2352.61%52.0-/+
01011 00.42100.2600.1305.51%52.0-/+
01100 76.6676.6643.3376.61%57.0-/+
01101 00.00176.6633.3366.61%57.0-/+
01110 00.81176.8733.9366.91%52.0-/+
01111 33.33176.6643.3376.61%57.0-/+

10000 08.6608.6604.3307.61%52.0-/+
10001 02.00108.6604.3307.61%52.0-/+
10010 00.51176.6733.8361.91%52.0-/+
10011 04.33107.6653.3376.61%52.0-/+
10100 08.6608.6604.3376.61%5.0-/+
10101 02.00108.6604.3307.61%5.0-/+
10110 00.01133.3776.6333.81%52.0-/+
10111 04.33107.6653.3376.61%5.0-/+
11000 00.50100.0700.5305.71%52.0-/+
11001 00.0900.0600.0300.51%52.0-/+
11010 00.5876.6533.8261.41%52.0-/+
11011 00.8700.8700.935.91%52.0-/+
11100 76.6676.6643.3376.61%5.0-ot0
11101 00.00176.6633.3366.61%5.0-ot0
11110 00.5700.5705.7357.81%52.0-/+
11111 33.33176.6643.3376.61%5.0-ot0

3tiB

stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0

]4:6[1,2tiBybdetcelessiycneuqerF-1

0

7tiB

lamroN-0

daerpSretneC%52.0±delbanEmurtcepSdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

5

ICS9248-151

Third party brands and names are the property of their respective owners.

Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB

02

17KLCICP

6tiB

81

16KLCICP

5tiB

71

15KLCICP

4tiB

61

14KLCICP

3tiB

41

13KLCICP

2tiB

31

12KLCICP

1tiB

11

11KLCICP

0tiB

01

10KLCICP

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.

TIB#NIPDWPNOITPIRCSED

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB-1 )devreseR(
0tiB-1 )devreseR(

Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB441 1CIPAOI
4tiB541 0CIPAOI
3tiB-1 )devreseR(
2tiB-1 )devreseR(
1tiB741 1FER
0tiB841 0FER

Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)

Byte 3: Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB

-X#2SF

6tiB

-

0

84_42LES

zHM84=1zHM42=0

5tiB

6

1zHM84

4tiB

7

1zHM84_42

3tiB

9

1F_KLCICP

2tiB

72

12KLCPGA

1tiB

62

11KLCPGA

0tiB

32

10KLCPGA

TIB#NIPDWPNOITPIRCSED

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)

Note: Don’t write into this register, writing into this

register can cause malfunction

TIB#NIPDWPNOITPIRCSED

7tiB530

;#FUPC_LES

gninnureerfeblliw2KLCUPC=0

gninnureerfebtonlliw2KLCUPC=1

6tiB-1 )devreseR(
5tiB-X#4SF
4tiB-X#3SF
3tiB531 2KLCUPC
2tiB831 1KLCUPC
1tiB931 0KLCUPC
0tiB241 2CIPAOI