ICST AV9248F-146-T, ICS9248F-146-T Datasheet

ICS9248-146

Third party brands and names are the property of their respective owners.

Integrated
Circuit
Systems, Inc.

Block Diagram

9248-146 RevA- 4/23/01

Recommended Application:

Single chip clock solution for SIS630S chipsets.

Output Features:

• 3- CPUs @ 2.5V

• 13 - SDRAM @ 3.3V

• 6- PCI @3.3V,

• 2 - AGP @ 3.3V

• 1- 48MHz, @3.3V fixed.

• 1- 24/48MHz, @3.3V selectable by I

2

C

(Default is 24MHz)

• 2- REF @3.3V, 14.318MHz.

Features:

• Up to 166MHz frequency support

• Support FS0-FS3 trapping status bit for I

2

C read back.

• Support power management: CPU, PCI, SDRAM stops
and Power down Mode form I

2

C programming.

• Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).

• Uses external 14.318MHz crystal

Skew Specifications:

• CPU - CPU: < 175ps

• SDRAM - SDRAM < 250ps (except SDRAM12)

• PCI - PCI: < 500ps

• CPU (early) - PCI: 1-4ns (typ. 2ns)

Functionality

Pin Configuration

48-Pin 300mil SSOP

* These inputs have a 120K pull down to GND.

1

These are double strength.

Frequency Generator & Integrated Buffers for Celeron & PII/III™

VDDA

(AGPSEL)REF0

*(FS3)REF1

GND

X1
X2

VDDPCI

*(FS1)PCICLK_F

*(FS2)PCICLK0

PCICLK1
PCICLK2
PCICLK3
PCICLK4

GND

VDDAGP
AGPCLK0
AGPCLK1

GND
GND

*(FS0)48MHz

*(MODE)24_48MHz

VDD48

S DATA

SCLK

1

1

*

VDDL
CPUCLK0
CPUCLK1
CPUCLK2
GND
VDDSDR
SDRAM0
SDRAM1
SDRAM2
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR

ICS9248-146

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK (2:0)

SDRAM (12:0)

PCICLK (4:0)

AGP (1:0)

PCICLK_F

2

5

13

3

2

X1

X2

XTAL
OSC

CPU

DIVDER

SDRAM
DIVDER

PCI

DIVDER

Stop

Stop

Stop

S DATA

SCLK

FS(3:0)

PD#

PCI_STOP#

CPU_STOP#

SDRAM_STOP#

MODE

AGP_SEL

Control

Logic

Config.

Reg.

/ 2

REF(1:0)

AGP

DIVDER

0 0 0 0 66.67 66.67 33.33 66.67 50.00
0 0 0 1 100.00 100.00 33.33 66.67 50.00
0 0 1 0 166.67 166.67 33.33 66.66 55.56
0 0 1 1 133.33 133.33 33.33 66.67 50.00
0 1 0 0 66.67 100.00 33.33 66.67 50.00
0 1 0 1 100.00 66.67 33.33 66.67 50.00
0 1 1 0 100.00 133.33 33.33 66.67 50.00
0 1 1 1 133.33 100.00 33.33 66.67 50.00
1 0 0 0 112.00 112.00 33.60 67.20 56.00
1 0 0 1 124.00 124.00 31.00 62.00 46.50

1 0 1 0 138.00 138.00 34.50 69.00 51.75
1 0 1 1 150.00 150.00 30.00 60.00 50.00
1 1 0 0 66.67 133.33 33.33 66.67 50.00

1 1 0 1 100.00 150.00 30.00 60.00 50.00
1 1 1 0 150.00 100.00 30.00 60.00 50.00

1 1 1 1 160.00 120.00 30.00 60.00 48.00

FS3 FS2 FS1 FS0 CPU SDRAM PCICLK

AGP SEL

= 0

AGP SEL

= 1

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-146

Third party brands and names are the property of their respective owners.

The ICS9248-146 is the single chip clock solution for
Desktop/Notebook designs using the SIS 630S style chipset.
It provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-146
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.

General Description

Pin Configuration

Power Groups

Analog

VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL

Digital

VDDPCI = PCICLK_F , PCICLK
VDDSDR = SDRAM
VDDAGP=AGP , REF

EDOM

12niP

72niP82niP03niP13niP

011MARDS01MARDS9MARDS8MARDS

1#POTS_UPC#POTS_ICP#POTS_MARDS#DP

MODE Pin Power Management Control Input

PIN NUMBER PIN NAME TYPE DESCRIPTION

1, 7, 15, 22, 25,

35, 43

VDD PWR

3.3V Pow er supply for S DRAM output buffers, PCI output buffers,
reference out

p

ut buffers and 48M Hz output

AGPSEL IN AG P frequency select pin.

REF0 OUT 14.318 MHz reference clock.

FS3 IN Frequency select pin.

REF1 OUT 14.318 MHz reference clock.

4, 14, 18, 19, 29,

32, 39, 44

GN D PWR Ground pin for 3V outputs.

5 X1 IN Crystal input,nominally 14.318M Hz.

6 X2 OUT Crystal output, nominally 14.318M Hz.

FS1 IN Frequency select pin.

PCICLK_F OUT PCI clock output, not affected by P CI_STOP#

FS2 IN Frequency select pin.

PCICLK0 OUT PCI clock output.

13, 12, 11, 10 PCICLK (4:1) OUT PCI clock outputs.

17, 16, AGP (1:0) OU T AG P outputs defined as 2X PCI. These may not be stopped.

FS0 IN Frequency select pin.

48MH z OUT 48MH z output clock

MODE IN

Pin 27, 28, 30, & 31 function select pins
0=Deskto

p

1=Mobile mode

24_48MH z OUT Clock output for super I/O/USB default is 24M Hz

23 SDATA I/O

Data

p

in for I2C circuitry 5V tolerant

24 SCLK IN

Clock

p

in of I2C circuitry 5V tolerant

CPU_STOP# IN

Stops all PCICLK s besides the PCICLK_F clocks at logic 0 level, when input
is low and M ODE

p

in is in M ob ile mode

SDRAM11 OUT SD RAM clock output

PCI_STOP# IN

Stops all CPUCLKs clocks at logic 0 level, when input is low and M OD E pin
is in M obile mode

SDRAM10 OUT SD RAM clock output

SDR AM 9 OU T SD RAM clock output

SDRAM_STOP# IN

Stops all SD RAM clocks at logic 0 level, when input is low and MOD E pin
is in M obile mode

PD# IN

Asynchronous active low input pin used to pow er down the device into a low
pow er state. The internal clocks are disabled and the VCO and the crys tal are
stopped. The latency of the power down will not be greater than 3ms.

SDR AM 8 OU T SD RAM clock output

26 33, 34, 36, 37,

38, 40, 41, 42

SDRAM (12, 7:0) OUT SDRAM clock outputs

45, 46, 47 CPUCLK (2:0) OUT CPU clock outputs.

48 VD DL PWR Pow er pin for the CPUCLKs. 2.5V

31

20

2

8

9

21

3

30

27

28

3

ICS9248-146

Third party brands and names are the property of their respective owners.

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note: PWD = Power-Up Default

Note1:

Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.

I

2

C is a trademark of Philips Corporation

tiBnoitpircseDDWP

2tiB

4:7tiB

2tiB

7tiB6tiB5tiB4tiB

00000
1etoN

3SF2SF1SF0SFUPCMARDSICP

PGA

0=LES

PGA

1=LES

egatnecerPdaerpS

0000 0 76.6676.6633.3376.6600.05daerpSnwoD%5.0-ot0
0000 1 00.00100.00133.3376.6600.05daerpSnwoD%5.0-ot0
000 10 76.66176.66133.3366.6665.55daerpSretneC%52.0-/+
000 1 1 33.33133.33133.3376.6600.05daerpSnwoD%5.0-ot0
0010 0 76.6600.00133.3376.6600.05daerpSnwoD%5.0-ot0
0010 1 00.00176.6633.3376.6600.05daerpSnwoD%5.0-ot0
00110 00.00133.33133.3376.6600.05daerpSnwoD%5.0-ot0
0011 1 33.33100.00133.3376.6600.05daerpSnwoD%5.0-ot0
01000 00.21100.21106.3302.7600.65daerpSretneC%52.0-/+
0100 1 00.42100.42100.1300.2605.64daerpSretneC%52.0-/+
01010 00.83100.83105.4300.9657.15daerpSretneC%52.0-/+
01011 00.05100.05100.0300.0600.05daerpSretneC%52.0-/+
01100 76.6633.33133.3376.6600.05daerpSnwoD%5.0-ot0
0110 1 00.00100.05100.0300.0600.05daerpSretneC%52.0-/+
01110 00.05100.00100.0300.0600.05daerpSretneC%52.0-/+
01111 00.06100.02100.0300.0600.84daerpSretneC%52.0-/+

1000 0 00.30100.30133.4376.8600.05daerpSretneC%52.0-/+
1000 1 03.00103.00134.3378.6600.05daerpSretneC%52.0-/+
100 1 0 00.00200.00233.3376.6600.05daerpSretneC%52.0-/+
100 1 1 37.33137.33134.3378.6651.05daerpSretneC%52.0-/+
1010 0 00.30133.73133.4376.8605.15daerpSretneC%52.0-/+
1010 1 33.73100.30133.4376.8605.15daerpSretneC%52.0-/+
101 1 0 78.6603.00134.3378.6651.05daerpSretneC%52.0-/+
101 1 1 37.33103.00134.3378.6651.05daerpSretneC%52.0-/+
1100 0 00.01100.01100.3300.6600.55daerpSretneC%52.0-/+
1100 1 00.51100.51105.4300.9605.75daerpSretneC%52.0-/+
110 1 0 00.04100.04100.5300.0705.25daerpSretneC%52.0-/+
110 1 1 05.10105.10138.3376.7600.05daerpSretneC%52.0-/+
1110 0 03.00137.33134.3378.6651.05daerpSretneC%52.0-/+
1110 1 00.50100.04100.5300.0705.25daerpSretneC%52.0-/+
11110 00.50105.75105.1300.3605.25daerpSretneC%52.0-/+
1111 1 33.53105.10138.3376.7657.05daerpSretneC%52.0-/+

3tiB

stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0

4:72,tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

delbanEmurtcepSdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

4

ICS9248-146

Third party brands and names are the property of their respective owners.

Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-1 devreseR
6tiB-1 devreseR
5tiB311 4KLCICP
4tiB211 3KLCICP
3tiB111 2KLCICP
2tiB011 1KLCICP
1tiB91 0KLCICP
0tiB81 F_KLCICP

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.

TIB#NIPDWPNOITPIRCSED

7tiB-1 devreseR
6tiB121 zHM84_42
5tiB021 zHM84
4tiB621 21MARDS
3tiB721 11MARDS
2tiB821 01MARDS
1tiB031 9MARDS
0tiB131 8MARDS

Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-X )kcabdaeR(3SF
6tiB-X )kcabdaeR(2SF
5tiB-X )kcabdaeR(1SF
4tiB-X )kcabdaeR(0SF
3tiB211FER
2tiB310FER
1tiB711 1KLCPGA
0tiB611 0KLCPGA

Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB331 7MARDS
6tiB431 6MARDS
5tiB631 5MARDS
4tiB731 4MARDS
3tiB831 3MARDS
2tiB041 2MARDS
1tiB141 1MARDS
0tiB241 0MARDS

TIB#NIPDWPNOITPIRCSED

7tiB-1

84_42leS

)zHM84:0,zHM42:1(
6tiB-1 devreseR
5tiB-1 devreseR
4tiB-1 devreseR
3tiB741 0KLCUPC
2tiB641 1KLCUPC
1tiB541 2KLCUPC
0tiB-1 devreseR

5

ICS9248-146

Third party brands and names are the property of their respective owners.

Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB-0 devreseR
6tiB-0 devreseR
5tiB-1 devreseR
4tiB-0 devreseR
3tiB-1 devreseR
2tiB-0 devreseR
1tiB-0 devreseR
0tiB-1 devreseR

Byte 7: Vendor ID Register
(1= enable, 0 = disable)

TIB#NIPDWPNOITPIRCSED

7tiB3,20 X2=1,X1=0htgnertsFER

6tiB540

lortnoC-potS-2KLCUPC

,2KLCUPClortnoclliw#POTS_UPC=0

wolsi#POTS_UPCfinevegninnureerfsi2KLCUPC=1
5tiB-X )kcabdaeR(LESPGA
4tiB-X )kcabdaeR(EDOM

3tiB-X )kcabdaeR(#POTS_UPC

2tiB-X )kcabdaeR(#POTS_ICP

1tiB-X )kcabdaeR(#POTS_MARDS

0tiB-0

elggoTdeepSPGA

,gnittestupnihctalybdenimretedeblliw)2nip(LESPGA=0

gnittestupnihctalfoetisoppoeblliwLESPGA=1