Integrated
Circuit
Systems, Inc.
ICS9248-141
Third party brands and names are the property of their respective owners.
Block Diagram
9248-141 Rev B 01/18/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KX133 style chipset
Output Features:
• 1 - Differential pair open drain CPU clocks
• 1 - Single-ended open drain CPU clock
• 13 - SDRAM @ 3.3V
• 6 - PCI @3.3V,
• 1 - 48MHz, @3.3V fixed.
• 1 - 24/48MHz @ 3.3V
• 2 - REF @3.3V, 14.318MHz.
Features:
• Up to 166MHz frequency support
• Support power management: CPU stop and Power down
Mode from I
2
C programming.
• Spread spectrum for EMI control
(± 0.25% center spread).
• Uses external 14.318MHz crystal
AMD - K7™ System Clock Chip
* Internal Pull-up Resistor of 120K to VDD
VDDREF
REF0/CPU_STOP#*
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER IN
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
S DATA
SCLK
REF1/FS2*
GND
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24/48MHz/FS1*
ICS9248-141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL24_48#
BUFFER IN
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
SDRAM (11:0)
PCICLK (4:0)
PCICLK_F
SDRAM_OUT
CPUCLKT (1:0)
CPUCLKC0
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
S DATA
SCLK
FS (3:0)
PD#
CPU_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
SDRAM
DRIVER
3SF2SF1SF0SF
UPC
)zHM(
KLCICP
)zHM(
0000 00.0900.03
0001 00.5976.13
0010 00.10176.33
0011 00.20100.43
0100 09.00175.33
0101 00.30133.43
0110 00.50100.53
0111 00.00133.33
1000 00.70176.53
1001 00.90133.63
1010 00.01176.63
1011 00.11100.73
1100 00.31176.73
1101 00.51133.83
1110 00.71100.93
1111 03.33133.33
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
2
ICS9248-141
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1FERDDVRWPV3.3lanimon,ylppusrewopLATX,FER
2
0FERTUO
REGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41
sdaolSUBASIrofreffub
#POTS_UPC
2,1
NI
MARDS&CKLCUPC,TKLCUPCstlahtupnisuonorhcnysasihT
.wolnevirdnehwlevel"0"cigolta)0:11(
,22,61,9,3
74,54,93,33
DNGRWPdnuorG
41XNI
kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC
2Xmorfrotsiser
52XTUO
daollanretnisaH.zHM813.41yllanimon,tuptuolatsyrC
)Fp63(pac
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7
F_KLCICPTUO
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.tnemeganam
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2,1
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51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI
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83,73,53,43
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1SF
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NI.tupnIdehctaL.niptcelesycneuqerF
62
zHM84TUOkcolctuptuozHM84
0SF
2,1
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7284DDVRWP.erocLLPdexifdnasreffubtuptuozHM84&42rofrewoP
04TUO_MARDSTUOreffubMARDSrofkcolcecnerefeR
14#DPNIwolevitca,pihcnwodsrewoP
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84
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2SF
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NItupnIdehctaL.niptcelesycneuqerF
3
ICS9248-141
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-141 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-141
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
7niP,EDOM
)tupnIdehctaL(
2niP
0
#POTS_UPC
)tupnI(
1
0FER
)tuptuO(
Power Groups
VDD48 = 48MHz, PLL2
VDDA = VDD for Core PLL
VDDREF = REF , Xtal
VDDPCI = PCI
VDDSDR = SDRAM
4
ICS9248-141
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
tiBnoitpircseDDWP
,2tiB
4:7tiB
tiB
2
tiB
7
tiB
6
tiB
5
tiB
4
KLCUPC
)zHM(
KLCICP
)zHM(
daerpS
egatnecerP
devreseR
00000 00.0900.03daerpSretneC%52.0±
00001 00.5976.13daerpSretneC%52.0±
00010 00.10176.33daerpSretneC%52.0±
00011 00.20100.43daerpSretneC%52.0±
00100 09.00175.33daerpSretneC%52.0±
00101 00.30133.43daerpSretneC%52.0±
00110 00.50100.53daerpSretneC%52.0±
00111 00.00133.33daerpSretneC%52.0±
01000 00.70176.53daerpSretneC%52.0±
01001 00.90133.63daerpSretneC%52.0±
01010 00.01176.63daerpSretneC%52.0±
01011 00.11100.73daerpSretneC%52.0±
01100 00.31176.73daerpSretneC%52.0±
01101 00.51133.83daerpSretneC%52.0±
01110 00.71100.93daerpSretneC%52.0±
01111 03.33133.33daerpSretneC%52.0±
10000 00.02100.04daerpSretneC%52.0±
10001 00.52152.13daerpSretneC%52.0±
100 10 00.03105.23daerpSretneC%52.0±
100 11 37.33134.33daerpSretneC%52.0±
10100 00.53157.33daerpSretneC%52.0±
1010 1 00.73152.43daerpSretneC%52.0±
10110 00.93157.43daerpSretneC%52.0±
10111 00.00133.33daerpSretneC%52.0±
11000 00.04100.53daerpSretneC%52.0±
11001 00.34157.53daerpSretneC%52.0±
11010 00.54152.63daerpSretneC%52.0±
11011 00.84100.73daerpSretneC%52.0±
11100 00.05105.73daerpSretneC%52.0±
11101 00.55157.83daerpSretneC%52.0±
11110 66.66176.14daerpSretneC%52.0±
11111 33.33133.33daerpSretneC%52.0±
3tiB
stupnIdehctaL,tceleserawdrahybdetcelessiycneuqerF-0
4:7,2tiBybdetcelessiycneuqerF-1
0
1tiB
lamroN-0
daerpSretneC%52.0±delbanEmurtcepSdaerpS-1
1
0tiB
gninnuR-0
stuptuollaetatsirT-1
0
5
ICS9248-141
Third party brands and names are the property of their respective owners.
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X#2SF
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-X#3SF
3tiB041 TUO_MARDS
2tiB-X #)#84_42LES(
1tiB44,341
htob(elbane0KLCUPC
dna"eurT".riaplaitnereffid
)"yratnemilpmoC
0tiB641 elbaneTKLCUPC
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-X#0SF
6tiB71 F_KLCICP
5tiB-1 )devreseR(
4tiB311 4KLCICP
3tiB211 3KLCICP
2tiB111 2KLCICP
1tiB011 1KLCICP
0tiB81 0KLCICP
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
TIB#NIPDWPNOITPIRCSED
7tiB821 7MARDS
6tiB921 6MARDS
5tiB131 5MARDS
4tiB231 4MARDS
3tiB431 3MARDS
2tiB531 2MARDS
1tiB731 1MARDS
0tiB831 0MARDS
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB-1 )devreseR(
4tiB-X #EDOM
3tiB-X#1SF
2tiB-1 )devreseR(
1tiB841 1FER
0tiB210FER
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
TIB#NIPDWPNOITPIRCSED
7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Don’t write into this register, writing into this
register can cause malfunction
TIB#NIPDWPNOITPIRCSED
7tiB-1 )devreseR(
6tiB-1 )devreseR(
5tiB621 zHM84
4tiB521 zHM84_42
3tiB711 11MARDS
2tiB811 01MARDS
1tiB021 9MARDS
0tiB121 8MARDS
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