ICST AV9248F-134-T, ICS9248F-134-T Datasheet

Integrated
Circuit
Systems, Inc.

ICS9248-134

Block Diagram

Frequency Timing Generator for PENTIUM II/III Systems

9248-134 Rev A 8/22/00

Pin Configuration

48-pin SSOP

*120K ohm pull-up to VDD on indicated inputs.

Recommended Application:

For Intel Camino Style Chipsets

Output Features:

• 3 - CPUs @ 2.5V, up to 180MHz.

• 1 - CPU/2 @ 2.5V.

• 3 - IOAPIC @ 2.5V, PCI or PCI/2

• 3 - 3V66MHz @ 3.3V.

• 11 - PCIs @ 3.3V

• 1 - 48MHz, @ 3.3V fixed

• 1 - 24/48MHz, @ 3.3V

Features:

• Support power management: Power down Mode
from I2C programming.

• Spread spectrum for EMI control
± 0.25% center spread).

• Uses external 14.318MHz crystal

Key Specifications:

• CPU Output Jitter: <250ps

• IOAPIC Output Jitter: <500ps

• 48MHz, 3V66, PCI Output Jitter: <500ps)

FREQ_APIC

SEL24_48#

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK (2:0)

IOAPIC (2:0)

PCICLK (9:0)

CPU/2

PCICLK_F

3V66 (2:0)

X1

X2

XTAL
OSC

CPU

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

S DATA

SCLK

FS (4:0)

PD#

Control

Logic

Config.

Reg.

/ 2

/ 2

REF (1:0)

Functionality

FS4 FS3 FS2 FS1 FS0 CPU PCI 3 V66 IOAPIC

0 0 0 0 0 103.00 34.33 68.67 17.17
0 0 0 0 1 105.00 35.00 70.00 17.50
0 0 0 1 0 100.45 33.483 66.967 16.742
0 0 0 1 1 100.90 33.63 67.27 16.82
0 0 1 0 0 107.10 35.700 71.400 17.850
0 0 1 0 1 109.00 36.33 72.67 18.17
0 0 1 1 0 112.00 37.34 74.67 18.67
0 0 1 1 1 114.00 28.50 57.00 14.25
0 1 0 0 0 116.00 29.00 58.00 14.50
0 1 0 0 1 118.00 29.50 59.00 14.75
0 1 0 1 0 133.30 33.33 66.65 16.66
0 1 0 1 1 120.00 30.00 60.00 15.00
0 1 1 0 0 122.00 30.50 61.00 15.25
0 1 1 0 1 125.00 31.25 62.50 15.63
0 1 1 1 0 128.21 32.05 64.105 16.026
0 1 1 1 1 130.00 32.50 65.00 16.25
1 0 0 0 0 132.00 33.00 66.00 16.50
1 0 0 0 1 133.90 33.48 66.95 16.74
1 0 0 1 0 138.00 34.50 69.00 17.25
1 0 0 1 1 142.00 35.50 71.00 17.75
1 0 1 0 0 146.00 36.50 73.00 18.25
1 0 1 0 1 150.00 37.50 75.00 18.75
1 0 1 1 0 153.00 38.25 76.50 19.13
1 0 1 1 1 156.00 39.00 78.00 19.50
1 1 0 0 0 159.00 39.75 79.50 19.88
1 1 0 0 1 162.00 40.50 81.00 20.25
1 1 0 1 0 165.00 41.25 82.50 20.63
1 1 0 1 1 168.00 42.00 84.00 21.00
1 1 1 0 0 171.00 42.75 85.50 21.38
1 1 1 0 1 174.00 43.50 87.00 21.75
1 1 1 1 0 177.00 44.25 88.50 22.13
1 1 1 1 1 180.00 45.00 90.00 22.50

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

GND

REF0

*SEL24_48#/REF1

VDDREF

X1
X2

GND

*FS0/PCICLK_F

*FS1/PCICLK0

VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2

GND
PCICLK3
PCICLK4

VDDPCI
PCICLK5
PCICLK6

GND
PCICLK7
PCICLK8
PCICLK9

VDDPCI

PD#

VDDL
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDL
CPU/2
GND
CPUCLK0
VDDL
CPUCLK1
CPUCLK2
GND
VDD66
3V66_0
3V66_1
3V66_2
GND66
S DATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48

ICS9248-134

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

2

ICS9248-134

Pin Descriptions

The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.

Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-134
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.

The CPU/2 clocks are inputs to the DRCG.

General Description

Pin number Pin name Type Description

1, 7, 13, 19, 25, 31,

36, 41, 45

GND PWR Ground pins

2 REF0 OUT 14.318MHz reference clock outputs at 3.3V

REF1 OUT 14.318MHz reference clock outputs at 3.3V
SEL24_48 IN Logic input to select 24 or 48MHz for pin 26 output

4, 10, 16, 23,

28, 35

VDD PWR Power pins 3.3V

5 X1 IN XTAL_IN 14.318MHz crystal input
6 X 2 OUT XTA L_O UT Crystal output

PCICLK_F OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not
affected b

y

the PCI_STOP# input.
FS0 IN Logic - input for frequency selection
PCICLK0 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS1 IN Logic - input for frequency selection
PCICLK1 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS2 IN Logic - input for frequency selection
PCICLK2 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS3 IN Logic - input for frequency selection

14, 15, 17, 18, 20,

21, 22

PCICLK (9:3) OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24 PD# IN

This asynchronous input powers dow n the chip w hen drive
active(Low ). The internal PLLs are disabled and all the output clocks
are held at a Low state.

26 24_48MHz OUT

24 or 48MHz output selectable by

SEL24_48# (0=48MHz 1=24M Hz)
48MHz OUT Fixed 48MHz clock output. 3.3V
FS4 IN Logic - input for frequency selection

29 SCLK IN

Clock in

p

ut of I2C inpu

t

30 SDATA I/O

Data

p

in for I2C circuitry 5V tolerant

32, 33, 34 3V66 (2:0) OUT

3.3V clock outputs. These outputs are stopped when CPU_STOP#

is driven active..

37, 38, 40 CPUCLK (2:0) OUT Host bus clock output at 2.5V.

42 CPU/2 OUT 2.5V clock outputs at 1/2 CPU frequency.
39, 43, 48 VDDL PWR Power pins for the CPU, CPU/2 & IOAPIC clocks. 2.5V
44, 46, 47 IOAPIC (2:0) OUT IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.

27

12

3

8

9

11

3

ICS9248-134

Byte 0: Functionality and frequency select register (Default = 0)

Serial Configuration Command Bitmap

Note 1:

Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.

tiBnoitpircseDDWP

tiB

4:7,2

2tiB

4SF

7tiB

3SF

6tiB

2SF

5tiB

1SF

4tiB

0SF

UPC2/UPCICP66V3CIPAOI

devreseR

1etoN

00000 00.30105.1533.4376.8671.71
00001 00.50105.2500.5300.0705.71
00010 54.001522.05384.33769.66247.61
00011 09.00154.0536.3372.7628.61
00100 01.701055.35007.53004.17058.71
00101 00.90105.4533.6376.2771.81
00110 00.21100.6543.7376.4776.81
00111 00.41100.7505.8200.7552.41
01000 00.61100.8500.9200.8505.41
01001 00.81100.9505.9200.9557.41
01010 03.33156.6633.3356.6666.61
01011 00.02100.0600.0300.0600.51
01100 00.22100.1605.0300.1652.51
01101 00.52105.2652.1305.2636.51
01110 12.821501.4650.23501.46620.61
01111 00.03100.5605.2300.5652.61

10000 00.23100.6600.3300.6605.61
10001 09.33159.6684.3359.6647.61
10010 00.83100.9605.4300.9652.71
10011 00.24100.1705.5300.1757.71
10100 00.64100.3705.6300.3752.81
10101 00.05100.5705.7300.5757.81
10110 00.35105.6752.8305.6731.91
10111 00.65100.8700.9300.8705.91
11000 00.95105.9757.9305.9788.91
11001 00.26100.1805.0400.1852.02
11010 00.56105.2852.1405.2836.02
11011 00.86100.4800.2400.4800.12
11100 00.17105.5857.2405.5883.12
11101 00.47100.7805.3400.7857.12
11110 00.77105.8852.4405.8831.22

11111 00.08100.0900.5400.0905.22

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

4:7,2tiBybdetcelessiycneuqerF-1

0

1tiB

delbasidmurtcepSdaerpS-0

delbanemurtcepsdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

4

ICS9248-134

Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)

Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)

Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Byte 4: PCI Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

tiB#niPDWPnoitpircseD

7tiB041 0KLCUPC
6tiB831 1KLCUPC
5tiB731 2KLCUPC
4tiB241 2/UPC

3tiB741 0CIPAOI

2tiB641 1CIPAOI

1tiB441 2CIPAOI

0tiB-X )devreseR(

tiB#niPDWPnoitpircseD

7tiB811 7KLCICP
6tiB711 6KLCICP
5tiB511 5KLCICP
4tiB411 4KLCICP
3tiB211 3KLCICP
2tiB111 2KLCICP
1tiB91 1KLCICP
0tiB81 F_KLCICP

tiB#niPDWPnoitpircseD

7tiB431 0_66V3
6tiB331 1_66V3
5tiB231 2_66V3
4tiB-X#1SF
3tiB311FER
2tiB210FER
1tiB-X#3SF
0tiB-X#2SF

tiB#niPDWPnoitpircseD

7tiB621 zHM84_42
6tiB721 zHM84
5tiB-X#0SF
4tiB-1 )devreseR(
3tiB221 01KLCICP
2tiB121 9KLCICP
1tiB021 8KLCICP
0tiB-X#4SF

Byte 5: Active/Inactive Register
(1= enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

Byte6: Active/Inactive Register
(1= enable, 0 = disable)

Note: Don’t write into this register, writing into this register

can cause malfunction

tiB#niPDWPnoitpircseD

7tiB-1 )etoN(devreseR
6tiB-1 )etoN(devreseR
5tiB-1 )etoN(devreseR
4tiB-1 )etoN(devreseR
3tiB-1 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-1 )etoN(devreseR

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.