Datasheet AV9248F-134-T, ICS9248F-134-T Datasheet (ICST)

Integrated
Circuit
Systems, Inc.

ICS9248-134

Block Diagram

Frequency Timing Generator for PENTIUM II/III Systems

9248-134 Rev A 8/22/00

Pin Configuration

48-pin SSOP

*120K ohm pull-up to VDD on indicated inputs.

Recommended Application:

For Intel Camino Style Chipsets

Output Features:

• 3 - CPUs @ 2.5V, up to 180MHz.

• 1 - CPU/2 @ 2.5V.

• 3 - IOAPIC @ 2.5V, PCI or PCI/2

• 3 - 3V66MHz @ 3.3V.

• 11 - PCIs @ 3.3V

• 1 - 48MHz, @ 3.3V fixed

• 1 - 24/48MHz, @ 3.3V

Features:

• Support power management: Power down Mode
from I2C programming.

• Spread spectrum for EMI control
± 0.25% center spread).

• Uses external 14.318MHz crystal

Key Specifications:

• CPU Output Jitter: <250ps

• IOAPIC Output Jitter: <500ps

• 48MHz, 3V66, PCI Output Jitter: <500ps)

FREQ_APIC

SEL24_48#

PLL2

PLL1

Spread

Spectrum

48MHz

24_48MHz

CPUCLK (2:0)

IOAPIC (2:0)

PCICLK (9:0)

CPU/2

PCICLK_F

3V66 (2:0)

X1

X2

XTAL
OSC

CPU

DIVDER

IOAPIC

DIVDER

PCI

DIVDER

3V66

DIVDER

S DATA

SCLK

FS (4:0)

PD#

Control

Logic

Config.

Reg.

/ 2

/ 2

REF (1:0)

Functionality

FS4 FS3 FS2 FS1 FS0 CPU PCI 3 V66 IOAPIC

0 0 0 0 0 103.00 34.33 68.67 17.17
0 0 0 0 1 105.00 35.00 70.00 17.50
0 0 0 1 0 100.45 33.483 66.967 16.742
0 0 0 1 1 100.90 33.63 67.27 16.82
0 0 1 0 0 107.10 35.700 71.400 17.850
0 0 1 0 1 109.00 36.33 72.67 18.17
0 0 1 1 0 112.00 37.34 74.67 18.67
0 0 1 1 1 114.00 28.50 57.00 14.25
0 1 0 0 0 116.00 29.00 58.00 14.50
0 1 0 0 1 118.00 29.50 59.00 14.75
0 1 0 1 0 133.30 33.33 66.65 16.66
0 1 0 1 1 120.00 30.00 60.00 15.00
0 1 1 0 0 122.00 30.50 61.00 15.25
0 1 1 0 1 125.00 31.25 62.50 15.63
0 1 1 1 0 128.21 32.05 64.105 16.026
0 1 1 1 1 130.00 32.50 65.00 16.25
1 0 0 0 0 132.00 33.00 66.00 16.50
1 0 0 0 1 133.90 33.48 66.95 16.74
1 0 0 1 0 138.00 34.50 69.00 17.25
1 0 0 1 1 142.00 35.50 71.00 17.75
1 0 1 0 0 146.00 36.50 73.00 18.25
1 0 1 0 1 150.00 37.50 75.00 18.75
1 0 1 1 0 153.00 38.25 76.50 19.13
1 0 1 1 1 156.00 39.00 78.00 19.50
1 1 0 0 0 159.00 39.75 79.50 19.88
1 1 0 0 1 162.00 40.50 81.00 20.25
1 1 0 1 0 165.00 41.25 82.50 20.63
1 1 0 1 1 168.00 42.00 84.00 21.00
1 1 1 0 0 171.00 42.75 85.50 21.38
1 1 1 0 1 174.00 43.50 87.00 21.75
1 1 1 1 0 177.00 44.25 88.50 22.13
1 1 1 1 1 180.00 45.00 90.00 22.50

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

GND

REF0

*SEL24_48#/REF1

VDDREF

X1
X2

GND

*FS0/PCICLK_F

*FS1/PCICLK0

VDDPCI
*FS2/PCICLK1
*FS3/PCICLK2

GND
PCICLK3
PCICLK4

VDDPCI
PCICLK5
PCICLK6

GND
PCICLK7
PCICLK8
PCICLK9

VDDPCI

PD#

VDDL
IOAPIC0
IOAPIC1
GND
IOAPIC2
VDDL
CPU/2
GND
CPUCLK0
VDDL
CPUCLK1
CPUCLK2
GND
VDD66
3V66_0
3V66_1
3V66_2
GND66
S DATA
SCLK
VDD48
48MHz/FS4*
24_48MHz
GND48

ICS9248-134

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

2

ICS9248-134

Pin Descriptions

The ICS9248-134 is a main clock synthesizer chip for Pentium II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used with a Direct Rambus Clock Generator(DRCG) chip such as the
ICS9212-01.

Spread Spectrum may be enabled by driving the SPREAD# pin active. Spread spectrum typically reduces system EMI by 8dB
to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-134
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.

The CPU/2 clocks are inputs to the DRCG.

General Description

Pin number Pin name Type Description

1, 7, 13, 19, 25, 31,

36, 41, 45

GND PWR Ground pins

2 REF0 OUT 14.318MHz reference clock outputs at 3.3V

REF1 OUT 14.318MHz reference clock outputs at 3.3V
SEL24_48 IN Logic input to select 24 or 48MHz for pin 26 output

4, 10, 16, 23,

28, 35

VDD PWR Power pins 3.3V

5 X1 IN XTAL_IN 14.318MHz crystal input
6 X 2 OUT XTA L_O UT Crystal output

PCICLK_F OUT

Free running PCI clock at 3.3V. Synchronous to CPU clocks. Not
affected b

y

the PCI_STOP# input.
FS0 IN Logic - input for frequency selection
PCICLK0 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS1 IN Logic - input for frequency selection
PCICLK1 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS2 IN Logic - input for frequency selection
PCICLK2 OUT PCI clock output at 3.3V. Synchronous to CPU clocks.
FS3 IN Logic - input for frequency selection

14, 15, 17, 18, 20,

21, 22

PCICLK (9:3) OUT PCI clock outputs at 3.3V. Synchronous to CPU clocks.

24 PD# IN

This asynchronous input powers dow n the chip w hen drive
active(Low ). The internal PLLs are disabled and all the output clocks
are held at a Low state.

26 24_48MHz OUT

24 or 48MHz output selectable by

SEL24_48# (0=48MHz 1=24M Hz)
48MHz OUT Fixed 48MHz clock output. 3.3V
FS4 IN Logic - input for frequency selection

29 SCLK IN

Clock in

p

ut of I2C inpu

t

30 SDATA I/O

Data

p

in for I2C circuitry 5V tolerant

32, 33, 34 3V66 (2:0) OUT

3.3V clock outputs. These outputs are stopped when CPU_STOP#

is driven active..

37, 38, 40 CPUCLK (2:0) OUT Host bus clock output at 2.5V.

42 CPU/2 OUT 2.5V clock outputs at 1/2 CPU frequency.
39, 43, 48 VDDL PWR Power pins for the CPU, CPU/2 & IOAPIC clocks. 2.5V
44, 46, 47 IOAPIC (2:0) OUT IOAPIC clocks at 2.5V. Synchronous with CPUCLKs.

27

12

3

8

9

11

3

ICS9248-134

Byte 0: Functionality and frequency select register (Default = 0)

Serial Configuration Command Bitmap

Note 1:

Default at power-up will be latched logic inputs to define frequency, as displayed by Bit 1.

tiBnoitpircseDDWP

tiB

4:7,2

2tiB

4SF

7tiB

3SF

6tiB

2SF

5tiB

1SF

4tiB

0SF

UPC2/UPCICP66V3CIPAOI

devreseR

1etoN

00000 00.30105.1533.4376.8671.71
00001 00.50105.2500.5300.0705.71
00010 54.001522.05384.33769.66247.61
00011 09.00154.0536.3372.7628.61
00100 01.701055.35007.53004.17058.71
00101 00.90105.4533.6376.2771.81
00110 00.21100.6543.7376.4776.81
00111 00.41100.7505.8200.7552.41
01000 00.61100.8500.9200.8505.41
01001 00.81100.9505.9200.9557.41
01010 03.33156.6633.3356.6666.61
01011 00.02100.0600.0300.0600.51
01100 00.22100.1605.0300.1652.51
01101 00.52105.2652.1305.2636.51
01110 12.821501.4650.23501.46620.61
01111 00.03100.5605.2300.5652.61

10000 00.23100.6600.3300.6605.61
10001 09.33159.6684.3359.6647.61
10010 00.83100.9605.4300.9652.71
10011 00.24100.1705.5300.1757.71
10100 00.64100.3705.6300.3752.81
10101 00.05100.5705.7300.5757.81
10110 00.35105.6752.8305.6731.91
10111 00.65100.8700.9300.8705.91
11000 00.95105.9757.9305.9788.91
11001 00.26100.1805.0400.1852.02
11010 00.56105.2852.1405.2836.02
11011 00.86100.4800.2400.4800.12
11100 00.17105.5857.2405.5883.12
11101 00.47100.7805.3400.7857.12
11110 00.77105.8852.4405.8831.22

11111 00.08100.0900.5400.0905.22

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

4:7,2tiBybdetcelessiycneuqerF-1

0

1tiB

delbasidmurtcepSdaerpS-0

delbanemurtcepsdaerpS-1

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

4

ICS9248-134

Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)

Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)

Byte 3: 3V66 Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

Byte 4: PCI Active/Inactive Register
(1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

tiB#niPDWPnoitpircseD

7tiB041 0KLCUPC
6tiB831 1KLCUPC
5tiB731 2KLCUPC
4tiB241 2/UPC

3tiB741 0CIPAOI

2tiB641 1CIPAOI

1tiB441 2CIPAOI

0tiB-X )devreseR(

tiB#niPDWPnoitpircseD

7tiB811 7KLCICP
6tiB711 6KLCICP
5tiB511 5KLCICP
4tiB411 4KLCICP
3tiB211 3KLCICP
2tiB111 2KLCICP
1tiB91 1KLCICP
0tiB81 F_KLCICP

tiB#niPDWPnoitpircseD

7tiB431 0_66V3
6tiB331 1_66V3
5tiB231 2_66V3
4tiB-X#1SF
3tiB311FER
2tiB210FER
1tiB-X#3SF
0tiB-X#2SF

tiB#niPDWPnoitpircseD

7tiB621 zHM84_42
6tiB721 zHM84
5tiB-X#0SF
4tiB-1 )devreseR(
3tiB221 01KLCICP
2tiB121 9KLCICP
1tiB021 8KLCICP
0tiB-X#4SF

Byte 5: Active/Inactive Register
(1= enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-0 )etoN(devreseR
6tiB-0 )etoN(devreseR
5tiB-0 )etoN(devreseR
4tiB-0 )etoN(devreseR
3tiB-0 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-0 )etoN(devreseR

Byte6: Active/Inactive Register
(1= enable, 0 = disable)

Note: Don’t write into this register, writing into this register

can cause malfunction

tiB#niPDWPnoitpircseD

7tiB-1 )etoN(devreseR
6tiB-1 )etoN(devreseR
5tiB-1 )etoN(devreseR
4tiB-1 )etoN(devreseR
3tiB-1 )etoN(devreseR
2tiB-1 )etoN(devreseR
1tiB-1 )etoN(devreseR
0tiB-1 )etoN(devreseR

Notes:

1. Inactive means outputs are held LOW and are disabled
from switching.

5

ICS9248-134

Absolute Maximum Ratings

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V

Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.

Electrical Characteristics - Input/Supply/Common Output Parameters

TA = 0 - 70º C; VDD = 3.3 V +/-5%; V

DDL

= 2.5 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input High Voltage V

IH

2V

DD

+0.3 V

Input Low Voltage V

IL

VSS-0.3 0.8 V

Input High Current I

IH

VIN = V

DD

0.1 5

µ

A

Input Low Current I

IL1

VIN = 0 V; Inputs with no pull-up resistors -5 2.0

µ

A

Input Low Current I

IL2

VIN = 0 V; Inputs with pull-up resistors -200 -100

µ

A

Operating I

DD3.3OP100CL

= 0 pF; Select @ 100 MHz 71 160 mA

Supply Current I

DD3.3OP133CL

= 0 pF; Select @ 133 MHz 76 160 mA

Input frequency F

i

VDD = 3.3 V; 11 14.318 16 MHz

Input Capacitance

1

C

IN

Logic Inputs 5 pF

C

INX

X1 & X2 pins 27 36 45 pF

Transition Time

1

T

trans

To 1st crossing of target Freq. 3 ms

Settling Time

1

T

s

From 1st crossing to 1% target Freq. 5 ms

Clk Stabilization

1

T

STAB

From VDD = 3.3 V to 1% target Freq.

3ms

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - Input/ Suppl y/Common Output Parameters

TA = 0 - 70º C; VDD = 3.3 V +/-5%; V

DDL

= 2.5 V +/-5% (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Operating I

DD2.5OP100CL

= 0 pF; Select @ 100 MHz 15 75 mA

Supply Current I

DD2.5OP133CL

= 0 pF; Select @ 133 MHz 18 90 mA

Power Down

Supply Curren

t

1

Guaranteed by design, not 100% tested in production.

µA

I

DD2.5PD

CL = 0 pF; PWRDWN# = 0

272 400

6

ICS9248-134

Group Offset

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

GROUP OFFSET MEASUREMENT LOADS MEASURE POINTS

CPU to 3V66 0.0-1.5 ns; CPU leads. CPU @ 20pF, 3V66 @ 30pF CPU @ 1.25V, 3V66 @ 1.5V

3V66 to PCI 0.5-4.0 ns; 3V66 leads. 3V66 @ 30pF, PCI @ 30pF 3V66 @ 1.5V, PCI @ 1.5V

CPU to IOAPIC 0.5-4.0 ns; CPU leads. CPU @ 20pF, IOAPIC @ 20pF CPU @ 1.25V, IOAPIC @ 1.25V

CPU to PCI 0.5-4.0 ns; CPU leads. CPU @ 20pF, PCI @ 30pF CPU @ 1.25V, PCI @ 1.5V

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - CPUCLK

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP2B

VO = V

DD

*(0.5) 13.5 30 45 Ω

Output Impedance

1

R

DSN2B

VO = V

DD

*(0.5) 13.5 32 45 Ω

Output High Voltage V

OH2BIOH

= -12.0 mA 2 2.24 V

Output Low Voltage V

OL2BIOL

= 12.0 mA 0.31 0.4 V

Output High Current I

OH2B

VOH = 1.7 V -31 -19 mA

Output Low Current I

OL2B

VOL = 0.7 V 19 25 mA

Rise Time

1

t

r2B

VOL = 0.4 V, VOH = 2.0 V 1.1 1.6 ns

Fall Time

1

t

f2B

VOH = 2.0 V, VOL = 0.4 V 1.4 1.8 ns

Dut

y Cy

cle

1

d

t2B

VT = 1.25 V; CPU frequencies < 135 MHz 45 50 55

%

Skew

1

t

sk2B

VT = 1.25 V 53 175 ps
V

T

= 1.25 V; CPU frequencies <135 MHz 179 275

V

T

= 1.25 V; CPU frequencies >=135 MHz

231 350

1

Guaranteed by design, not 100% tested in production.

Jitter, Cycle-to-cycle

1

ps

t

jcyc-cyc2B

Electrical Characteristics - CPU/2

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP2B

VO = V

DD

*(0.5) 13.5 30 45 Ω

Output Impedance

1

R

DSN2B

VO = V

DD

*(0.5) 13.5 31 45 Ω

Output High Voltage V

OH2B

IOH = -12.0 mA 2 2.2 V

Output Low Voltage V

OL2B

IOL = 12.0 mA 0.31 0.4 V

Output High Current I

OH2B

VOH = 1.7 V -31 -19 mA

Output Low Current I

OL2B

VOL = 0.7 V 19 26 mA

Rise Time

1

t

r2B

VOL = 0.4 V, VOH = 2.0 V 1.1 1.6 ns

Fall Time

1

t

f2B

VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns

Duty Cycle

1

d

t2B

VT = 1.25 V 45 49 55 %
V

T

= 1.25 V; CPU frequencies <135 MHz 227 275

V

T

= 1.25 V; CPU frequencies >=135 MHz

306 350

1

Guaranteed by design, not 100% tested in production.

Jitter, Cycle-to-cycle

1

ps

t

jcyc-cyc2B

7

ICS9248-134

Electrical Characteristics - 3V66

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP1

VO = V

DD

*(0.5) 12 24 55 Ω

Output Impedance

1

R

DSN1

VO = V

DD

*(0.5) 12 23 55 Ω

Output High Voltage V

OH1

IOH = -11 mA 2.4 3.1 V

Output Low Voltage V

OL1

IOL = 9.4 mA 0.17 0.4 V

Output High Current I

OH1

VOH = 2.0 V -51 -22 mA

Output Low Current I

OL1

VOL = 0.8 V 16 41 mA

Rise Time

1

t

r1

VOL = 0.4 V, VOH = 2.4 V 1.4 2 ns

Fall Time

1

t

f1

VOH = 2.4 V, VOL = 0.4 V 1.5 2 ns

Duty Cycle

1

d

t1

VT = 1.5 V 45 50 55 %

Skew

1

t

sk1

VT = 1.5 V 89 250 ps

Jitter, Cycle-to-cycle

1

T

jcyc-cyc1

VT = 1.5 V

173 500 ps

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - PCICLK

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP1

VO = V

DD

*(0.5) 12 24 55 Ω

Output Impedance

1

R

DSN1

VO = V

DD

*(0.5) 12 23 55 Ω

Output High Voltage V

OH1

IOH = -11 mA 2.4 3.1 V

Output Low Voltage V

OL1

IOL = 9.4 mA 0.16 0.4 V

Output High Current I

OH1

VOH = 2.0 V -50 -22 mA

Output Low Current I

OL1

VOL = 0.8 V 16 42 mA

Rise Time

1

t

r1

VOL = 0.4 V, VOH = 2.4 V 1.8 2.5 ns

Fall Time

1

t

f1

VOH = 2.4 V, VOL = 0.4 V 1.5 2.5 ns

Duty Cycle

1

d

t1

VT = 1.5 V 455055%
V

T

= 1.5 V, PCICLK

(F:7)

260 350

V

T

= 1.5 V, PCICLK

(8:10)

211 250

V

T

= 1.5 V, PCICLK

(F:10)

466 600

Jitter, Cycle-to-cycle

1

T

jcyc-cyc1

VT = 1.5 V

280 500 ps

1

Guaranteed by design, not 100% tested in production.

Skew Window

1

t

sk1

ps

8

ICS9248-134

Electrical Characteristics - 48 MHz, 24_48 MHz

TA = 0 - 70ºC; VDD = 3.3 V +/-5%; V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP5

VO = V

DD

*(0.5) 20 47 60 Ω

Output Impedance

1

R

DSN5

VO = V

DD

*(0.5) 20 44 60 Ω

Output High Voltage V

OH5

IOH = -16 mA 2.4 2.62 V

Output Low Voltage V

OL5

IOL = 9 mA 0.3 0.4 V

Output High Current I

OH5

VOH = 2.0 V -27 -22 mA

Output Low Current I

OL5

VOL = 0.8 V 16 22 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 2.1 4 ns

Fall Time

1

t

f5

VOH = 2.4 V, VOL = 0.4 V 2.2 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 51 55 %

Jitter, Cycle-to-cycle

1

T

jcyc-cyc5

VT = 1.5 V

375 500 ps

1

Guaranteed by design, not 100% tested in production.

Electrical Characteristics - REF

TA = 0 - 70ºC; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP5

VO = V

DD

*(0.5) 20 48 60 Ω

Output Impedance

1

R

DSN5

VO = V

DD

*(0.5) 20 44 60 Ω

Output High Voltage V

OH5

IOH = -16 mA 2.4 2.6 V

Output Low Voltage V

OL5

IOL = 9 mA 0.3 0.4 V

Output High Current I

OH5

VOH = 2.0 V -26 -22 mA

Output Low Current I

OL5

VOL = 0.8 V 16 22 mA

Rise Time

1

t

r5

VOL = 0.4 V, VOH = 2.4 V 2.1 4 ns

Fall Time

1

t

f5

VOH = 2.4 V, VOL = 0.4 V 2.2 4 ns

Duty Cycle

1

d

t5

VT = 1.5 V 45 53 55 %

Jitter, Cycle-to-cycle

1

T

jcyc-cyc5

VT = 1.5 V

839 1000 ps

1

Guaranteed by design, not 100% tested in production.

9

ICS9248-134

Electrical Characteristics - IOAPIC

TA = 0 - 70º C; VDD = 3.3 V +/-5%, V

DDL

= 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Output Impedance

1

R

DSP4B

VO = V

DD

*(0.5) 13.5 26 45 Ω

Output Impedance

1

R

DSN4B

VO = V

DD

*(0.5) 13.5 31 45 Ω

Output High Voltage V

OH4B

IOH = -12.0 mA 2 2.24 V

Output Low Voltage V

OL4B

IOL = 12.0 mA 0.31 0.4 V

Output High Current I

OH4B

VOH = 1.7 V -31 -19 mA

Output Low Current I

OL4B

VOL = 0.7 V 19 26 mA

Rise Time

1

T

r4B

VOL = 0.4 V, VOH = 2.0 V 1.6 2 ns

Fall Time

1

T

f4B

VOH = 2.0 V, VOL = 0.4 V 1.6 2 ns

Duty Cycle

1

D

t4B

VT = 1.25 V 45 49 55 %

Skew

1

t

sk4B

VT = 1.25 V 139 250 ps

Jitter, Cycle-to-cycle

1

T

jcyc-cyc4B

VT = 1.25 V

245 500 ps

1

Guaranteed by design, not 100% tested in production.

10

ICS9248-134

Power Management Features:

Note:

1. LOW means outputs held static LOW as per latency requirement next page.

2. On means active.

3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.

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zHM84

csOsOCV

0WOLWOLWOLWOLWOLWOLWOLFFOFFO

1NONONONONONONONONO

Power Management Requirements:

Note:

1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.

2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.

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fosegdegnisirfo.oN

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11

ICS9248-134

1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for

verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.

2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)

3. The input is operating at 3.3V logic levels.

4. The data byte format is 8 bit bytes.

5. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.

6. At power-on, all registers are set to a default condition, as shown.

General I2C serial interface information

The information in this section assumes familiarity with I2C programming.

For more information, contact ICS for an I2C programming application note.

How to Write:

 Controller (host) sends a start bit.
 Controller (host) sends the write address D2

(H)

 ICS clock will acknowledge
 Controller (host) sends a dummy command code
 ICS clock will acknowledge
 Controller (host) sends a dummy byte count
 ICS clock will acknowledge
 Controller (host) starts sending first byte (Byte 0)

through byte 5

 ICS clock will acknowledge each byte one at a time.
 Controller (host) sends a Stop bit

How to Read:

 Controller (host) will send start bit.
 Controller (host) sends the read address D3

(H)

 ICS clock will acknowledge
 ICS clock will send the byte count
 Controller (host) acknowledges
 ICS clock sends first byte (Byte 0) through byte 5
 Controller (host) will need to acknowledge each byte
 Controller (host) will send a stop bit

Notes:

Controller (Host) ICS (Slave/Receiver)

Start Bit

Address

D3

(H)

AC

K

Byte Count

ACK

Byte

0

ACK

Byte 1

ACK

Byte

2

ACK

Byte

3

ACK

Byte 4

ACK

Byte

5

ACK

Stop Bit

How to Read:

Controller (Host) ICS (Slave/Receiver)

Start Bit
Address

D2

(H)

AC

K

Dummy Command Code

AC

K

Dummy Byte Count

AC

K

Byte 0

AC

K

Byte 1

ACK

Byte 2

AC

K

Byte 3

AC

K

Byte 4

AC

K

Byte 5

AC

K

Stop Bit

How to Write:

12

ICS9248-134

PD# Timing Diagram

The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.

Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).

2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.

3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.

4. The shaded sections on the VCO and the Crystal signals indicate an active clock.

5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.

13

ICS9248-134

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

Ordering Information

ICS9248yF-134-T

Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type

F=SSOP

Revision Designator (will not correlate with datasheet revision)

Device Type (consists of 3 or 4 digit numbers)
Prefix

ICS, AV = Standard Device

Example:

ICS XXXX y F - PPP - T

MIN MA X MIN MAX

A 2.413 2.794 .095 .110

A1 0.203 0.406 .008 .016

b 0.203 0.343 .008 .0135
c 0.127 0.254 .005 .010
D
E 10.033 10.668 .395 .420

E1 7.391 7.595 .291 .299

e 0.635 BASIC 0.025 BASIC
h 0.381 0.635 .015 .025
L 0.508 1.016 .020 .040
N

α

0° 8° 0° 8°

V A RIATIONS

MIN MA X MIN MAX

28 9.398

9.652

.370 .380

34 11.303

11.557

.445 .455

48 15.748

16.002

.620 .630

56 18.288

18.542

.720 .730

64 20.828

21.082

.820 .830

J E D E C MO-118
DO C # 10-0034

6/1/00

REV B

SYMBOL

SEE VARIATIONS

SEE VARIATIONS

In Millimeter s

COMMON DIMENSIONS

In Inc hes

COMMON DIMENSIONS

SEE VARIATIONS

N

D mm.

D (inch)

SEE VARIATIONS