ICST AV9248F-131-T, ICS9248F-131-T Datasheet

Integrated Circuit Systems, Inc.

ICS9248-131

Block Diagram

Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation

9248-131 Rev B 7/17/00

Pin Configuration

48-Pin SSOP

* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

VDDF

*REF0/CPU2.5_3.3#

GND

X1 X2

VDDPCI

*PCICLK_F/FS1

*PCICLK0/FS2

GND PCICLK1 PCICLK2 PCICLK3 PCICLK4

VDDA

BUFFERIN

GND

*CPU_STOP#/SDRAM11

*PCI_STOP#/SDRAM10

VDDSDR

*AGP_STOP#/SDRAM9

*PD#/SDRAM8

GND

SDATA

SCLK

VDDAGP AGP0 AGP1 GND CPUCLK0 CPUCLK1 VDDL CPUCLK2

SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND 48MHz/FS0* AGP_F/MODE*

SDRAM12 GND

ICS9248-131

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

Recommended Application:

ALI - Aladdin V



- mobile style chipsets

Output Features:

 3 - CPUs @ 2.5/3.3V, up to 100MHz.  3 - AGPCLK @ 3.3V  13 - SDRAM @ 3.3V  6 - PCI @ 3.3V  1 - 48MHz, @ 3.3V fixed.  1 - REF @ 3.3V, 14.318MHz.

Features:

 Support power management: CPU, PCI, AGP stop and

Power down Mode from I2C programming.  Spread spectrum for EMI control.  Uses external 14.318MHz crystal  FS pins for frequency select

Key Specifications:

 CPU  CPU: <250ps  AGP  PCI: <550ps  CPU(early)-PCI: 1-4ns, Center 2-6ns

Frequency Generator & Integrated Buffers for Celeron & PII/III™

CPU2.5_3.3#

PLL2

PLL1

Spread

Spectrum

48MHz

CPUCLK (2:0)

PCICLK (4:0)

AGP (1:0)

AGP_F

PCICLK_F

XTAL OSC

CPU

DIVDER

PCI

DIVDER

AGP

DIVDER

Stop

SDATA

SCLK

FS (2:0)

PD#

PCI_STOP#

CPU_STOP#

SDRAM_STOP#

AGP-STOP#

MODE

Control

Logic

Config.

Reg.

REF

BUFFERIN

SDRAM (12:0)

1 1 1 100 33.33 66.67 1 1 0 95.25 31.75 63.50 1 0 1 83.3 33.30 66.60 1 0 0 97 32.33 6 4.66 0 1 1 91.5 30.50 61.00 0 1 0 96.22 32.07 64.15 0 0 1 66.67 33.33 66.67 0 0 0 60 30.00 6 0.00

PCI

(MHz)

FS2 FS1 FS0

CPU, SDRAM

(MHz)

AGP

(MHz)

Functionality

Note: REF & IOAPIC = 14.318MHz

Power Groups

Analog Digital

VDDF VDDPCI VDDA VDDSDR

VDDAGP

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

ICS9248-131

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

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51NIREFFUBNI.sreffubMARDSrofniptupnI

#POTS_UPC

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#POTS_PGANI

woltupninehwlevel"0"cigoltaskcolcPGAstlahtupnisuonorhcnysasihT

0PGAtceffatonseoD)0=EDOM,edoMeliboMni(

9MARDSTUOtuptuokcolcMARDS

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lanretni&latsyrc,OCVehtspotStupninwoDrewoPsuonorehcnysasihT

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tnarelotV5yrtiucricC

42KLCSNIIfonipkcolC

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F_PGATUO#POTS_PGAybdetceffatoN,tuptuotroPcihparGdecnavdA

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24LDDVRWPlanimonV3.3roV5.2rehtie,UPCrofylppuS

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ICS9248-131

5.2_#3.3UPC

leveltupnI

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rofdetceleSreffuB

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1DDVV5.2

0DDVV3.3

CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.

Power Management Functionality

Mode Pin - Power Management Input Control

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)TUPNI(

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)TUPNI(

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)TUPNI(

11MARDS )TUPTUO(

01MARDS )TUPTUO(

9MARDS

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8MARDS

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KLCUPC stuptuO

KLCICP

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CSO

OCV

PGA

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101 woLdeppotSgninnuRgninnuRgninnuRgninnuRgninnuR 111 gninnuRgninnuRgninnuRgninnuRgninnuRgninnuR 110 gninnuRwoLdeppotSgninnuRgninnuRgninnuRgninnuR

011 gninnuRgninnuRgninnuRgninnuRgninnuRwoLdeppotS

General Description

The ICS9248-131 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions.

Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-131 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.

Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.

ICS9248-131

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

I2C is a trademark of Philips Corporation

Note 1. Default at Power-up will be for latched logic inputs to define frequency. Bits 4, 5, 6 are default to 001, and if bit

3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycle.

Note: PWD = Power-Up Default

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR( 6tiB-X#2SF 5tiB-X#1SF 4tiB041 )tcanI/tcA(21MARDS 3tiB-1 )devreseR( 2tiB141 )tcanI/tcA(2KLCUPC 1tiB341 )tcanI/tcA(1KLCUPC 0tiB441 )tcanI/tcA(0KLCUPC

tiB#niPDWPnoitpircseD

7tiB-X #3.3_5.2UPC 6tiB71 )tcanI/tcA(F_KLCICP 5tiB-X#0SF 4tiB311 )tcanI/tcA(4KLCICP 3tiB211 )tcanI/tcA(3KLCICP 2tiB111 )tcanI/tcA(2KLCICP 1tiB011 )tcanI/tcA(1KLCICP 0tiB81 )tcanI/tcA(0KLCICP

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

Bit PWD

Bit7 Bit2

0,0 0,1 1,0 1,1

Bit6 Bit5 Bit4 CPU Clock PCI AGP

111 100 33.33 66.67 110 95.25 31.75 63.50 101 83.3 33.30 66.60 100 97 32.33 64.66 011 91.5 30.50 61.00 010 96.22 32.07 64.15 001 66.67 33.33 66.67 000 60 30.00 60.00

Bit 1

Bit 0

1 - Tristate all out

uts

0 - Frequency is selected by hardware select, Latched inputs 1 - Frequency is selected by Bit 6:4 (above)

0 to -0.5 Down Spread Spectrum Modulat ion +/- 0.375% Center S

read Spectrum Modulation

0 - Normal 1 - Spread Spectrum Enabled 0 - Running

Description

Note1

001

Bit 3

Bit 6:4

Bit 7,2 0,0

Spread Spectrum Method +/- 0.25% Center Spread Spectrum Modulation +/- 0.15% Center Spread Spectrum Modulation

ICS9248-131

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

tiB#niPDWPnoitpircseD

7tiB821 )tcanI/tcA(7MARDS 6tiB921 )tcanI/tcA(6MARDS

5tiB131 )tcanI/tcA(5MARDS 4tiB231 )tcanI/tcA(4MARDS 3tiB431 )tcanI/tcA(3MARDS 2tiB531 )tcanI/tcA(2MARDS 1tiB731 )tcanI/tcA(1MARDS 0tiB831 )tcanI/tcA(0MARDS

Byte 4: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable)

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

tiB#niPDWPnoitpircseD

7tiB521 )evitcanI/evitcA(F_PGA 6tiB-1 )devreseR( 5tiB-1 )devreseR( 4tiB-1 )devreseR(

3tiB711

)tcanI/tcA(11MARDS

)ylnOedoMpotkseD(

2tiB811

)tcanI/tcA(01MARDS

)ylnOedoMpotkseD( 1tiB021 )tcanI/tcA(9MARDS 0tiB121 )tcanI/tcA(8MARDS

tiB#niPDWPnoitpircseD

7tiB-1 )devreseR( 6tiB-1 )devreseR( 5tiB-1 )devreseR( 4tiB741 )tcanI/tcA(0PGA 3tiB-1 )devreseR( 2tiB-XEDOM 1tiB641 )tcanI/tcA(1PGA 0tiB21 )tcanI/tcA(0FER

Byte 6: Optional Register for Possible Furture Requirements

Notes:

1. Byte 6 is reserved by Integrated Circuit Systems for futue applications.

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7tiB-1 )devreseR(

6tiB-1 )devreseR(

5tiB-1 )devreseR(

4tiB-1 )devreseR(

3tiB-1 )devreseR(

2tiB-1 )devreseR(

1tiB-1 )devreseR(

0tiB-1 )devreseR(

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