ICST AV9248F-127-T, ICS9248F-127-T Datasheet

Integrated
Circuit
Systems, Inc.

General Description Features

ICS9248-127

Block Diagram

Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation

Frequency Generator & Integrated Buffers for PENTIUM/Pro

TM

9248-127 Rev C 8/18/00

Pin Configuration

• Up to 124MHz frequency support.

• Spread Spectrum for EMI control 0 to -0.5% down
spread and ±0.25% center spread

• Serial I2C interface for Power Management,
Frequency Select, Spread Spectrum.

• Provides the following system clocks

- 4-CPUs @ 3.3V, up to 124MHz.

- 13-SDRAMs @3.3V, up to 124MHz
(including SDRAM_F)

- 6-PCI (including 1 free running, PCICLK_F)
@3.3V, CPU/2 or CPU/3.

- 1-24MHz @3.3V fixed.

- 1-48MHz @3.3V fixed.

- 2-REF @3.3V, 14.318MHz.

• Efficient Power management scheme through PCI
and STOP CLOCKS.

48-Pin SSOP

Power Groups

VDDCPU, GNDCPU = CPUCLKS, CPUCLK_F
VDDSDR, GNDSDR = SDRAMCLKS, SDRAM_F
VDDPCI, GNDPCI = PCICLKS, PCICLK_F
VDD48 = 48MHz, 24MHz
VDDREF, GNDREF = REF, X1, X2

* Internal Pull-up Resistor of 240K to VDD

The ICS9248-127 is the single chip clock solution for Desktop
designs using the VIA MVP4 and Aladdin 7 style chipset. It
provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
127 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.

VDDREF

*PCI_STOP#/REF0

GND

X1
X2

VDDPCI

*MODE/PCICLK_F

*FS3/PCICLK0

GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4

VDDPCI

BUFFER IN

GND

SDRAM11
SDRAM10

VDDSDR
SDRAM9
SDRAM8

GND

SD ATA

SCLK

REF1/FS2*
VDDCPU
CPUCLK_F
CPUCLK0
GND
CPUCLK1
CPUCLK2
CLK_STOP#
GND
SDRAM_F
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
48MHz/FS0*
24MHz/FS1*

ICS9248-127

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

CLK_STOP#

PCI_STOP#

PLL2

PLL1

Spread

Spectrum

48MHz

24MHz

CPUCLK_F

CPUCLK (2:0)

SDRAM (11:0)

PCICLK (4:0)

PCICLK_F

SDRAM_F

X1

X2

BUFFER IN

XTAL
OSC

PCI
CLOCK
DIVDER

STOP

STOP

STOP

S DATA

SCLK

FS(3:0)

MODE

Control

Logic

Config.

Reg.

/ 2

REF (1:0)

LATCH

POR

2

3

12

5

4

4

ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

2

ICS9248-127

Pin Descriptions

Notes:

1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to

program logic Hi to VDD or GND for logic low.

REBMUNNIPEMANNIPEPYTNOITPIRCSED

,03,72,91,41,6,1

74,63

DDVRWPylppusrewopV3.3

2

0FERTUO

REGNORTSehtsituptuoFERsihT.kcolcecnereferzhM813.41

sdaolSUBASIrofreffub

#POTS_ICP

1

NI

woltupninehw,level0cigoltaskcolcKLCICPstlaH

)0=EDOM,edomelibomnI(

,22,61,9,3

44,04,33

DNGRWPdnuorG

41XNI

kcabdeefdna)Fp63(pacdaollanretnisah,tupnilatsyrC

2Xmorfrotsiser

52XTUO.zHM813.41yllanimon,tuptuolatsyrC

7

F_KLCICPTUO

rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF

.tnemeganam

EDOM

2,1

NI

.edoMeliboM=0,edoMpotkseD=1,niptcelesnoitcnuf2nip

.tupnIdehctaL

8

3SF

1

NI.tupnIdehctaL.niptcelesycneuqerF

0KLCICPTUO

wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP

)ylraeUPC(

01,11,21,31)1:4(KLCICPTUO

wekssn4-1htiwskcolcUPCotsuonorehcnyS.stuptuokcolcICP

)ylraeUPC(

51NIREFFUBNI.stuptuoMARDSrofsreffuBtuonaFottupnI

,82,12,02,81,71
,53,43,23,13,92

83,73

)0:11(MARDSTUO

nipNIREFFUBmorfstuptuoreffuBtuonaF,stuptuokcolcMARDS

.)tespihcybdellortnoc(

32ATADSO/IIrofnipataD

2

tnarelotV5yrtiucricC

42KLCSNIIfonipkcolC

2

tnarelotV5yrtiucricC

52

zHM42TUOkcolctuptuozHM42

1SF

2,1

NI.tupnIdehctaL.niptcelesycneuqerF

62

zHM84TUOkcolctuptuozHM84

0SF

2,1

NItupnIdehctaL.niptcelesycneuqerF

93F_MARDSTUO#POTS_UPCybdetceffatoN.tuptuokcolcMARDSgninnureerF

14#POTS_KLCNI

"0"cigoltaMARDS&KLCUPCstlahtupnisuonorhcnysasihT

.wolnevirdnehwlevel

54,34,24)0:2(KLCUPCTUOUPCDDVybderewop,stuptuokcolcUPC

64F_KLCUPCTUO#POTS_UPCehtybdetceffatoN.kcolcUPCgninnureerF

84

1FERTUO.kcolcecnereferzHM813.41

2SF

2,1

NItupnIdehctaL.niptcelesycneuqerF

3

ICS9248-127

Functionality

VDD1,2,3 = 3.3V±5%, TA=0 to 70°C
Crystal (X1, X2) = 14.31818MHz

Mode Pin - Power Management Input Control

3SF2SF1SF0SF

UPC

)zHM(

ICP

)zHM(
0000 00.42133.14
0001 00.02100.04
0010 99.41133.83
0011 99.90166.63
0100 00.50100.53
0101 13.3856.14
0110 00.0800.04
0111 00.5705.73
1000 00.00133.33
100 1 91.5937.13
10 10 13.3877.72
10 11 00.7933.23
1100 00.0900.03
1101 00.0700.53
1110 28.6614.33
1111 00.0600.03

EDOM

)tupnIdehctaL(

2niP

0

#POTS_ICP

)tupnI(

1

0FER

)tuptuO(

4

ICS9248-127

Byte0: Functionality and Frequency Select Register (default = 0)

Serial Configuration Command Bitmap

Note: PWD = Power-Up Default.

Note 1. Default at Power-up will be for latched logic inputs to define frequency.

I2C readback of the power up default indicate the revision ID code in bit 2,
6:4 as shown.

I2C is a trademark of Philips Corporation

tiBnoitpircseDDWP

7tiB

noitaludoMmurtcepSdaerpSretneC%52.0±-0

noitaludoMmurtcepSdaerpSnwoD%5.0-ot0-1

1

tiB

]4:6,2[

]4:6,2[tiB

KLCUPC

)zHM(

KLCICP
)zHM(

1etoN
010,0

000000.42133.14

100000.02100.04

010099.41133.83

110099.90166.63

001000.50100.53

101013.3856.14

011000.0800.04

111000.5705.73

000100.00133.33

100191.5937.13

010113.3877.72

110100.7933.23

001100.0900.03

101100.0700.53

011128.6614.33

111100.0600.03

3tiB

stupnidehctal,tceleserawdrahybdetcelessiycneuqerF-0

]4:6,2[tiBybdetcelessiycneuqerF-1

0

1tiB

lamroN-0

delbanEmurtcepSdaerpS-1

2etoN

1

0tiB

gninnuR-0

stuptuollaetatsirT-1

0

Note 2. To ensure normal operation, Bit 7 needs to be "0" when in non - spread spectrum

mode (Bit 1 = 0).

5

ICS9248-127

Notes:

1. Inactive means outputs are held LOW and are disabled from switching.

2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.

Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X #0SFdehctaL
6tiB71 )tcanI/tcA(F_KLCICP
5tiB-1 )devreseR(
4tiB311 )tcanI/tcA(4KLCICP
3tiB211 )tcanI/tcA(3KLCICP
2tiB111 )tcanI/tcA(2KLCICP
1tiB011 )tcanI/tcA(1KLCICP
0tiB81 )tcanI/tcA(0KLCICP

Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB-X #2SFdehctaL
6tiB641 )tcanI/tcA(F_KLCUPC
5tiB-1 )devreseR(
4tiB-1 )devreseR(
3tiB931 )tcanI/tcA(F_MARDS
2tiB241 )tcanI/tcA(2KLCUPC
1tiB341 )tcanI/tcA(1KLCUPC
0tiB541 )tcanI/tcA(0KLCUPC

Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)

tiB#niPDWPnoitpircseD

7tiB711 )evitcanI/evitcA(11MARDS
6tiB811 )evitcanI/evitcA(01MARDS
5tiB021 )evitcanI/evitcA(9MARDS
4tiB121 )evitcanI/evitcA(8MARDS
3tiB821 )evitcanI/evitcA(7MARDS
2tiB921 )evitcanI/evitcA(6MARDS
1tiB131 )evitcanI/evitcA(5MARDS
0tiB231 )evitcanI/evitcA(4MARDS