ICST AV9248F-110, ICS9248F-110 Datasheet
Integrated
Circuit
Systems, Inc.
ICS9248-110
Third party brands and names are the property of their respective owners.
Block Diagram
9248-110 Rev C 01/08/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
AMD-K7 based systems
Output Features:
• 3 differential pair open drain CPU clocks (2.7V external
pull-up; up to 150MHz achieviable through I
2
C)
• 2 - AGPCLK @ 3.3V
• 8 - PCI @3.3V, including 1 free running
• 1 - 48MHz @ 3.3V
• 1 - 24/48MHz @ 3.3V
• 2- REF @3.3V, 14.318MHz.
Features:
• Up to 150MHz frequency support
• Support power management: CPU, PCI, stop and Power
down Mode from I
2
C programming.
• Spread spectrum for EMI control -0.5% down spread
• Uses external 14.318MHz crystal
• FS pins for frequency select
Key Specifications:
• CPU – CPU: <250ps
• AGP-AGP: <250ps
• PCI – PCI: <400ps
• CPU - SDRAM_OUT: <400ps
• CPU-AGP <250ps
AMD-K7TM System Clock Chip
* Internal 120K pullup resistor on indicated inputs
** Internal 240K pullup resistor on indicated inputs
**FS0/REF0
**FS1/REF1
GNDREF
X1
X2
GNDPCI
PCICLK_F
PCICLK0
VDDPCI
PCICLK1
PCICLK2
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PCICLK6
VDDAGP
AGP0
AGP1
GNDAGP
VDD48
48MHz
SEL24_48#/24-48MHz
VDDREF
GNDSD
SDRAM_OUT
VDDSD
RESERVED
CPUCLKC2
CPUCLKT2
GNDCPU
CUCLKC1
CPUCLKT1
GND
CPUCLKC0
CPUCLKT0
RESERVED
VDD
GND
PCI_STOP#
CPU_STOP
PD#
SPREAD#
FS2*
S DATA
SCLK
GND48
ICS9248-110
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
FS (2:0)
SPREAD#
CPU_STOP#
X1
X2
OSC
PLL
CPU
STOP
PLL2
REF (1:0)
CPUCLKC (2:0)
CPUCLKT (2:0)
SDRAM_OUT
48MHz
PCICLK (6:0)
24_48MHz
PCICLK_F
PCI_STOP#
SEL24_48#
PD#
/ 2 / 3
PCI
STOP
X 2
/ 2
AGP (1:0)
0 0 0 90 30.00 60.00
0 0 1 95 31.67 63.33
0 1 0 100.99 33.66 67.33
0 1 1 115 38.33 76.67
1 0 0 100.7 33.57 67.13
1 0 1 103 34.33 68.67
1 1 0 105 35.00 70.00
1 1 1 110 36.67 73.33
PCI AGPFS2 FS1 FS0
CPU,
SDRAM
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS9248-110
Third party brands and names are the property of their respective owners.
Pin Descriptions
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52XTUOFp33pacdaollanretnisah,tuptuolatsyrCTUO_LATX
21,6ICPDNGRWPstuptuoICProfdnuorG
7F_KLCICPTUO
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.tupni
8,01,11,31,41,61,71)0:6(KLCICPTUOV3.3elbitapmocLTT.stuptuokcolcICP
51,9ICPDDVRWPV3.3yllanimon,stuptuoKLCICProfrewoP
81PGADDVRWPV3.3yllanimon,stuptuoPGArofrewoP
91,02)0:1(PGATUO.deppotsebtonyamesehT.ICPX2sadenifedstuptuoPGA
12PGADNGRWPstuptuokcolcPGArofdnuorG
43DDVRWPV3.3yllanimon,erocrofrewopdetalosI
33DNGRWPerocrofdnuorgdetalosI
2284DDVRWPV3.3yllanimonstuptuoCDF,BSUrofrewoP
32zHM84TUOtuptuozHM84
42
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42niproftuptuozHM84ro42stceleS
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zHM84-42TUO#84-42LEShguorhtelbatcelestuokcolcdexiF
5284DNGRWPstuptuozHM84rofdnuorG
62KLCSNIIroftupnikcolC
2
C
72ATADSO/IIrofnipataD
2
tnarelotV5yrtiucricC
822SFNIDDVotpu-llupsah,niptceleSycneuqerF
92#DAERPSNI
daerpSnwoD.WOLnehwerutaefmurtcepSdaerpSselbanE
zHK05=ycneuqerfnoitaludom%5.0
03#DPNI
erastuptuolla&LLPlanretnI.wolevitca,pihcnwodsrewoP
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13#POTS_UPCNI
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detressasinipsihtnehwHGIHnevirdsi
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23#POTS_ICPNI
F_KLCICP.wolnevirdnehwlevel"0"cigoltasuBICPstlaH
nipsihtybdetceffatonsi
64TUO_MARDSTUOreffubyaledorezMARDSrofkcolcecnerefeR
43DDVRWPerocrofrewopdetalosI
44,53DEVRESERC/NliarrewopUPCerutruF
63,93,24)0:2(TKLCUPCTUO
nepoesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT"
.pu-llupV5.1lanretxenadeenstuptuoniard
73,04,34)0:2(CKLCUPCTUO
esehT.tuptuoUPCriaplatnereffidfoskcolc"yrotnemelpmoC"
.pu_llupV5.1lanretxenadeenstuptuoniardnepo
14,83UPCDNGRWP.stuptuoKLCUPCrofdnuorG
54DSDDVRWPV3.3yllanimoN.nipTUO_MARDSrofrewoP
74DSDNGRWPsnipTUO_MARDSrofdnuorG
84FERDDVRWPV3.3yllanimon,2X,1X,FERrofrewoP
3
ICS9248-110
Third party brands and names are the property of their respective owners.
General Description
The ICS9248-110 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a
system when used with a Zero Delay Buffer Chip such as the ICS9179-06.
Spread spectrum may be enabled through I
2
C programming. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-110
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I
2
C interface allows changing functions, stop clock programming and frequency selection.
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-110. All other clocks will continue to run while the CPUCLKs clocks are
disabled. The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width
is a full pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPUCLKs inside the ICS9248-110.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
PCICLK
CPUCLKT
CPUCLKC
PCI_STOP# (High)
CPU_STOP#
PD# (High)
INTERNAL
CPUCLK
4
ICS9248-110
Third party brands and names are the property of their respective owners.
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-110. It is used to turn off the PCICLK (0:5) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-110 internally. PCICLK (0:5) clocks are stopped in a low state and
started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off
latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK
(Free-runningl)
CPU_STOP#
PWR_DWN#
PCICLK
(External)
PCI_STOP#
5
ICS9248-110
Third party brands and names are the property of their respective owners.
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-110 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
PD#
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