ICST AV9248BF-55, ICS9248BF-55 Datasheet

Integrated Circuit Systems, Inc.

General Description Features

ICS9248-55

Block Diagram

Pentium/Pro/IITM System Clock Chip

9248-55 Rev B 12/04/98

Pin Configuration

48-Pin SSOP

Pentium is a trademark on Intel Corporation.

 Generates system clocks for CPU, IOAPIC, PCI, plus

14.314 MHz REF (0:2), USB, and Super I/O  Supports single or dual processor systems  Supports Spread Spectrum modulation for CPU & PCI

clocks, down spread -0.5%

 Skew from CPU (earlier) to PCI clock (rising edges for

100/33.3MHz) 1.5 to 4ns  Two fixed outputs at 48MHz.  Separate 2.5V and 3.3V supply pins  2.5V or 3.3V output: CPU, IOAPIC  3.3V outputs: PCI, REF, 48MHz  No power supply sequence requirements  Uses external 14.318MHz crystal, no external load cap

required for CL=18pF crystal  48 pin 300 mil SSOP

The ICS9248-55 is a Clock Synthesizer chip for Pentium and PentiumPro CPU based Desktop/Notebook systems that will provide all necessary clock timing.

Features include four CPU and eight PCI clocks. Three reference outputs are available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, assuring that CPU and PCI clocks are stable within 2ms after power-up.

PD# pin enables low power mode by stopping crystal OSC and PLL stages. Other power management features include CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#, which stops PCICLK (0:6) clocks.

High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20pF loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.

The ICS9248-55 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply.

Power Groups

VDD = Supply for PLL core VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:6) VDD3 = 48MHz0, 48MHz1 VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3)

Ground Groups

GND = Ground for PLL core GND1 = REF (0:2), X1, X2 GND2 = PCICLK_F, PCICLK (0:6) GND3 = 48MHz0, 48MHz1 GNDL1 = IOAPIC (0:1) GNDL2 = CPUCLK (0:3)

ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.

* Internal Pull-down Resistor of 240K to GND. on indicated inputs

ICS9248-55

Pin Descriptions

Select Functions

Functionality CPU

PCI,

PCI_F

REF IOAPIC

48 MHz

Selection

Tristate HI - Z HI - Z HI - Z HI - Z HI - Z

Testmode T CLK/2

TCLK/6

TCLK

TCLK/2

Spread Spectrum Modulated2Modulated214.318MHz 14.318MHz 48.0MHz

PIN NUMBER PIN NAME TYPE DESCRIPTION

1, 2 REF0, REF1 OUT 14.318MHz clock output

3 GND1 PWR Ground for REF outputs 4X1IN

XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2

5 X2 OUT XTAL_OUT Crystal ou tput, has in ternal load cap 33pF

6, 12, 18 GND2 PWR Ground for PCI outputs

7 PCICLK_F OUT Free Running PCI output

8, 10, 11, 13, 14, 16, 17 PCICLK (0:6) OUT PCI clock outputs. TTL compatible 3.3V

9, 15 VDD2 PWR Power for PCICLK outputs, nominally 3.3V 19, 33 VDD PWR Isolat ed power for c ore, nom inally 3.3V 20, 32 GND PWR Isolated ground for core

21 VDD3 PWR Power for 48MHz outputs, nominally 3.3V

22, 23 48MHz (0:1) OUT 48MHz outputs

24 GND3 P WR Ground for 48MHz outputs

25, 26, 27 FS (0:2) IN Frequency Select pins

28 SPREAD# IN Enables Spread Spectrum feature when LOW 29 PD# IN Powers down chip, active low 30 CPU_STOP# IN Halts CPU clocks at logic "0" level when low

31 PCI_STOP# I N Halts PCI Bus at logic "0" level when low 37, 41 VDDL2 PWR Power for CPU outputs, nominally 2.5V 34, 38 GNDL2 PWR Ground for CPU outputs.

35, 36, 39, 40 CPUCLK (3:0) OUT CPU and Host clock outputs @ 2.5V

42 N/C - Not internally connected

43 GNDL1 PWR Ground for IOAPIC outputs 44, 45 IOAPIC (0:1) OUT IOAPIC outputs (14.318MHz) @ 2.5V

46 VDDL1 PWR Power for IOAPIC outputs, nominally 2.5V

SS_SEL IN

±.25% Spread Spectrum Selector at power up. Logic 0 for Downspread Logic 1 for Centerspread

REF2 OUT 14.318MHz clock output

48 VDD1 PWR Supply for REF (0:2), X1, X2, nominal 3.3V

FS2 FS1 FS0 CPU MHz PCI MHz

0 0 0 133 33.25 0 0 1 83.3 41.65 010 75 37.5 0 1 1 66.6 33.3

1 0 0 124 41.33 1 0 1 133 44.3 1 1 0 112 37.3 1 1 1 100 33.3

ICS9248-55

Power Management

ICS9248-55 Power Management Requirements

Clock Enable Configuration

Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up and power down operations using the PD# select pin will not cause clocks of a shorter or longer pulse than that of the running clock. The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. Board routing and signal loading may have a large impact on the initial clock distortion also.

Notes.

1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.

2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.

3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.

4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only. The REF and IOAPIC will be stopped independent of these.

SIGNAL SIGNAL STATE

Latency

No. of rising edges of free

running PCICLK

CPU_ STOP# 0 (Disabled)

1 (Enabled)

PCI_STOP# 0 (Disabled)

1 (Enabled)

PD# 1 (N ormal Op eration )

3ms

0 (Power Down)

2max

CPU_STOP# PCI_STOP# PWR_DWN# CPUCLK PCICLK

Other Clocks,

REF,

IOAPICs, 48 MHz 0 48 MHz 1

Crystal VCOs

X X 0 Low Low Stopped Off Off

0 0 1 Low Low Running Running Running 0 1 1 Low Run ning Running Running Runn ing

1 0 1 Running Low Runnin g Running Running 1 1 1 Running Running Running Running Running

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