ICST AV9179BF-01, ICS9179BF-01 Datasheet
Integrated
Circuit
Systems, Inc.
General Description Features
ICS9179B-01
Block Diagram
PentiumPro is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
Low Skew Buffers
9179B-01 Rev C 05/18/98
Pin Configuration
The ICS9179B-01 generates SDRAM clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro or Pentium II. An output enable is provided
for testability.
The device is a buffer with low output to output skew. This is
a Fanout buffer device, not using an internal PLL. This buffer
can also be a feedback to an external PLL stage for phase
synchronization to a master clock.
The individual clock outputs are addressable through I2C to
be enabled, or stopped in a low state for reduced EMI when
the lines are not needed.
High speed, low noise non-inverting (0:17) buffer for
SDRAM clock buffer applications.
Supports up to four SDRAM DIMMS
Synchronous clocks skew matched to 250ps window on
SDRAM.
I
2
C Serial Configuration interface to allow individual
clocks to be stopped.
Multiple VDD, VSS pins for noise reduction
Tri-state pin for testing
Custom configurations available
3.0V 3.7V supply range
48-pin SSOP package
48-Pin SSOP
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
2
ICS9179B-01
Pin Descriptions
Power Groups
VDD = Power supply for SDRAM buffer
VDDS = Power supply for I2C circuitry
PIN NUMBER PIN NAME TYPE DESCRIPTION
4, 5, 8, 9 SDRAM (0:3) OUT SDRAM Byte 0 clock outputs
1
13, 14, 17, 18 SDR AM (4:7) O UT SDRAM B yte 1 cloc k outpu ts
1
31, 32, 35, 36 SDRAM ( 8:11) OU T SDRAM Byte 2 clock outputs
1
40, 41, 44, 45 SDRAM (12:15) OUT SDRAM Byte 3 clock outputs
1
21, 28 SDRAM (16:17) OUT SDRAM clock outputs useable for feedback.
1
11 BUF_IN IN Input for buffers
38 OE IN Tri-states all outputs when held LOW. Has internal pull-up.
2
24 SDATA I /O Data pin for I2C circuitry
3
25 SCLK I/O Clock pin for I2C circuitry
3
3, 7, 12, 16, 20,
29, 33, 37, 42, 46
VDD PWR 3.3V Power supply for SDRAM buffer
6, 10, 15, 19, 22,
27, 30, 34, 39, 43
GND PW R Ground for SDRAM buffer
23 VDDS PWR 3.3V Power supply for I
2
C circuitry
26 GNDS PWR Ground for I
2
C circuitry
1, 2, 47, 48 N/C - Pins are not internally connected
Notes:
1. At power up all eighteen SDRAM outputs are enabled and active.
2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for
complete platform flexibility.
Ground Groups
GND = Ground for SDRAM buffer
GNDS = Ground for I2C circuitry
3
ICS9179B-01
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for SDRAM(0:17).
This pin operates at 3.3V volts. Clocks from the listed buffers
that it supplies will have a voltage swing from Ground to this
level. For the actual guaranteed high and low voltage levels
for the Clocks, please consult the DC parameter table in this
data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
SDRAM(0:17)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing of
the SDRAMs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I2C
The SDATA and SCLOCK Inputs are use to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook (1996)
should be followed.
BUF_IN
Input for Fanout buffers (SDRAM 0:17).
OE
OE tristates all outputs when held low.
VDDS
This is the power supply to I2C circuitry.
GNDS
This is the ground to I2C circuitry.
Technical Pin Function Descriptions
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