ICST AV9169M-01, AV9169F-01, ICS9169F-01, ICS9169M-01 Datasheet
Integrated
Circuit
Systems, Inc.
General Description
Features
XTAL OSC
BCLK(0:5)
PCLK(0:3)
OEN
REF(0:2)
48 MHz
SYNC
REG
PLL
CLOCK
GEN
PLL
CLOCK
GEN
X2
X1
FS0
FS1
Block Diagram
Pentium is a trademark of Intel Corporation
PowerPC is a trademark of Motorola Corporation
Frequency Generator and Integrated Buffers for Intel Pentium
and Pentium ProTM
µµ
µµ
µP's
ICS9169-01
The ICS9169-01 generates all clocks required for high speed
RISC or CISC microprocessor systems such as 486, Pentium/
Pentium Pro™, PowerPC™, etc. Four different reference
frequency multiplying factors are externally selectable with
smooth frequency transitions. These multiplying factors can
be customized for specific applications. A test mode is provided
to drive all clocks directly.
High drive BCLK outputs typically provide greater than 1V/
ns slew rate into 30pF loads. PCLK outputs typically provide
better than 1V/ns slew rate into 20pF loads while maintaining
50±5% duty cycle. The REF clock outputs typically provide
better than 0.5V/ns slew rates.
• Generates four processor, six bus, three 14.318 MHz
and one 48 MHz clock for ISA bus, audio, super I/O
and bus bridge devices
• Supports the Intel MARS chip set
• Synchronous clocks skew matched to 250ps window on
PCLKs and 500ps window on BCLKs
• Test clock mode eases system design
• Selectable multiplying ratios
• Custom configurations available
• Output frequency ranges to 100 MHz (depending on
option)
• 3.0V - 5.5 V supply range
• 28-pin SOIC and 28-pin SSOP (209-mil) packages
Applications
• Ideal for high-speed RISC or CISC systems such as 486,
Pentium, Pentium Pro, PowerPC, etc.
9169-01RevE 08/28/98
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
2
ICS9169-01
Pin Configuration
Pin Descriptions
Functionality
*VCO range is limited from 60 - 200 MHz
Note 1: BCLK buffers cannot be supplied with 5 volts (pins 14 and 20) if CPU and fixed frequencies (pins 1, 8, and 26) are being
supplied with 3.3 volts
PIN NUMBER PIN NAME TYPE DESCRIPTION
2X1IN
XTAL or external referenc e frequency in put. This input in cludes XTAL load
capacitance and feedba ck bias for a 12.16 MH z crystal, nominally 14.3181 8
3 X2 OUT XTAL output which includes XTAL load capacitance.
4, 11, 23 GND PWR Ground for logic, PCLK and fixed frequency output buffers.
17
GND PW R Ground for BCL K output buffers.
1, 8, 26 VDD PW R Power for logic, PCLK an d fixed frequency output buffers.
14, 20 VDD PW R Power fo r BCLK o utput buffers.
6, 7, 9, 10 PCLK(0:3) OUT
Processor clo ck outputs w hich are a multip le of the input refere nce frequency
as shown in the table above .
13, 12 FS(0:1) IN
Frequency multiplier select pins. See table above. These inputs have internal
pull-up devices.
15, 16, 18
19, 21, 22
BCLK (0:5) OUT Bus clock outputs are fixed at 1/2 the PCLK frequency.
5 OEN IN OEN tristates all outp uts when low. This inp ut has an internal p ull-up device.
24 48MHz OUT Fixed 48 M Hz clock (with 14 .318 MHz input).
28, 27, 25 REF(0:2) OUT
REF is a b uffered copy of th e crystal oscillator o r reference input clo ck,
nominally 14.31818 M Hz.
PCLK(0:3) BCLK(0:5) 48 MHz
VCO/2 PCLK/2 48 MHz
TCLK/2 TCLK/4 TCLK/2
28 Pin SOIC
28 Pin SSOP
FS1 FS0 *VCO X1, REF
(MHz)
PCLK(0:3)
(MHz)
0 0 230/33x X1 14.31818 50 (49.7)
0 1 212/23x X1 14.31818 66 (66.5)
1 0 176/21x X1 14.31818 60 (59.9)
1 1 Test mode TCLK TCLK/2
3
ICS9169-01
Absolute Maximum Ratings
.
Electrical Characteristics at 3.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stess
specifications only and functional operation of the device at these or any other conditions above those listed in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Stresses a
stess spec
operation
periods m
Supply Voltage.................................................................................................................................................................. 7.0 V
Logic Inputs ............................................................................................................................ GND - 0.5 V to VDD + 0.5 V
Ambient Operating Temperature ........................................................................................................................... 0 t o + 7 0 C
Storage T emperature......................................................................................................................................... -65 to +150 C
VDD = 3.0 - 3.7 V, TA = 0 - 70oC unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
DC Characteristics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Low Voltage V
IL --0.2VDD V
Input High Voltage V
IH 0.7VDD --V
Input Low Current I
IL VIN = 0 V -28.0 -10.5 -
µA
Input High Current I
IH VIN = VDD -5.0 - 5.0
µA
Output Low C urrent
1
IOL
VOL = 0.8 V;
for PCLKs & BCLKs
30.0 47. 0 - mA
Output Hi gh Curren t
1
IOH
VOL = 2.0 V; for
PCLKs & BCLKs
- -66.0 -42.0 mA
Output Low C urrent
1
IOL VOL=0.8V; for fixed CLKs 25.0 38. 0 - mA
Output Hi gh Curren t
1
IOH VOL=2.0V; for fixed CLKs - -47.0 - 30.0 mA
Output Low Vo ltage
1
VOL IOL = 15 mA; for PCLKs & BCLKs - 0.3 0.4 V
Output High Voltage
1
VOH
IOH = -30 mA;
for PCLKs & BCLKs
2.4 2.8 - V
Output Low Vo ltage
1
VOL IOL=12.5mA; for fixed CLKs - 0.3 0.4 V
Output High Voltage
1
VOH
IOH = -20mA;
for fixed CLKs
2.4 2.8 - V
Supply Current I
DD @ 66.5 MHz; all outputs unloaded - 55 110 mA
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